2014-3-12 FPGA学习-数码管 2

因为昨天那个用了130多个LE，太多了，所以今天想精简一下，顺便改成10进制的。

在修改代码中发现always后设置敏感变量用cnt_1ms 比用clk和rst_n消耗的LE要多10个左右。

在修改时还因为阻塞和非阻塞导致了bug：

display <= display + 16'd1;

if(display[3:0] >=4'd9)
begin
display <= display & 16'hfff0;
display[7:4] <= display[7:4] + 4'd1;

end

else

display <= display;

因为第二个display赋值用了非阻塞，导致了display将未+1前的display赋给自己，数字不再变化。

这次的LE用的还是很多，大概有110个，原谅我这个新手吧：

module leds(
clk, //50Mhz时钟
rst_n, //低电平复位
seg, //段选信号
bit //位选信号
);


input clk;
input rst_n;


output[7:0] seg;
output[7:0] bit;


reg[7:0] seg;
reg[3:0] bit;
reg[3:0] dis_seg;//段选辅助寄存器
reg[9:0] cnt_1s; //计时1s
reg[15:0] cnt_1ms; //计时1ms
reg[15:0] display; //显示的数字




//==========the 1ms gap ===================
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt_1ms <= 26'd0;
else if(cnt_1ms >= 16'd5000)
cnt_1ms <= 16'd0;
else
cnt_1ms <= cnt_1ms + 16'b1;
//==========the 1s gap====================
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt_1s <= 10'd0;
else if(cnt_1ms >= 16'd5000)
cnt_1s <= cnt_1s + 10'd1;
else if(cnt_1s>=10'd1000)
cnt_1s <= 10'd0;
else
cnt_1s <= cnt_1s;

//============显示数増一，位选循环=============
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
display <= 16'd0;
else if(cnt_1s >= 10'd1000)
begin
display <= display + 16'd1;

if(display[3:0] >=4'd9)
begin
display <= display & 16'hfff0;
display[7:4] <= display[7:4] + 4'd1;
if(display[7:4] >=4'd9)
begin
display <= display & 16'hff00;
display[11:8] <= display[11:8] + 4'd1;
if(display[11:8] >=4'd9)
begin
display <= display & 16'hf000;
display[15:12] <= display[15:12] + 4'd1;
if(display[15:12] >=4'd9)
begin
display <= 16'd0;
end
end
end
end





if(display[15:12] >=4'd9)
begin
display <= 16'd0;
end


end
else
display <= display;

if(!rst_n)
bit <= 4'b1110;
else if(cnt_1ms >= 16'd5000)
bit <= {bit[2:0],bit[3]};
else
bit <= bit;
end


//==========位选显示==========================
always@(bit)
begin
case(bit)
4'b1110 : dis_seg <= display[3:0];
4'b1101 : dis_seg <= display[7:4];
4'b1011 : dis_seg <= display[11:8];
4'b0111 : dis_seg <= display[15:12];
default   : dis_seg <= dis_seg;
endcase
end
//========片选显示===========================
always@(dis_seg)
begin
case(dis_seg)
4'h0 : seg <= 8'hc0;   // "0"
4'h1 : seg <= 8'hf9;   // "1"
4'h2 : seg <= 8'ha4;   // "2"
4'h3 : seg <= 8'hb0;   // "3"
4'h4 : seg <= 8'h99;   // "4"
4'h5 : seg <= 8'h92;   // "5"
4'h6 : seg <= 8'h82;   // "6"
4'h7 : seg <= 8'hf8;   // "7"
4'h8 : seg <= 8'h80;   // "8"
4'h9 : seg <= 8'h90;   // "9"
4'ha : seg <= 8'h88;   // "a"
4'hb : seg <= 8'h83;   // "b"
4'hc : seg <= 8'hc6;   // "c"
4'hd : seg <= 8'ha1;   // "d"
4'he : seg <= 8'h86;   // "e"
4'hf : seg <= 8'h8e;   // "f"
default : seg <= seg;
endcase
end


initial
begin
display <= 16'd0;
dis_seg <= 4'd0;
bit <= 4'b1110;
end


endmodule