FPGA之tft_lcd的显示

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一、TFT显示模式

<1>HV同步模式

时序图：
从时序图来看，它的显示模式与VGA基本上没有区别。

<2>DE同步模式

时序图：
从时序图看，没有场同步与行同步信号线，只有DE一条信号线。

<3>SPI模式

时序图：

<4>小知识

<5>RGB接口TFT-LCD分辨率

<6>注意

（1）使用DE模式时，仍然需要行场同步信号的配合，但行场同步信号可以不输出，在使用HE模式时，正常使用即可。
（2）正常模式下的PLL，输出时钟时不可直接输出PLL生成的时钟，需要用一个wire型信号赋值，即assign x = PLL_CLK，
（3）严格按照时序图来说，时钟应取反输出。

二、波形图(DE模式)

主频：33.3MHZ左右
器件：野火800*480的5寸屏
帧率：65HZ左右

三、代码及显示结果

数据模块：

module tft_data
(
    input       wire                sys_clk,//33.3Mhz,65HZ
    input       wire                rst,
    input       wire     [9:0]      x,
    input       wire     [9:0]      y,
    
    output      reg     [15:0]  data
);

localparam
    BLACK       =       16'h0000,
    RED         =       16'hf800,
    ORANGE      =       16'hfc00,
    YELLOW      =       16'hffe0,
    GREEN       =       16'h07e0,
    CYAN        =       16'h07ff,
    BLUE        =       16'h001f,
    PUPPLE      =       16'hf81f,
    WHITE       =       16'hffff,
    GRAY        =       16'hd69a;
    

always@(posedge sys_clk or negedge rst)
    if(rst == 1'd0)
        data <= BLACK;
    else if(x > 1'd0 && x <= 10'd80)
        data <= BLACK;
    else if(x > 10'd80 && x <= 10'd160)
        data <= RED;
    else if(x > 10'd160 && x <= 10'd240)
        data <= ORANGE;
    else if(x > 10'd240 && x <= 10'd320)
        data <= YELLOW;
    else if(x > 10'd320 && x <= 10'd400)
        data <= GREEN;
    else if(x > 10'd400 && x <= 10'd480)
        data <= CYAN;
    else if(x > 10'd480 && x <= 10'd560)
        data <= BLUE;
    else if(x > 10'd560 && x <= 10'd640)
        data <= PUPPLE;
    else if(x > 10'd640 && x <= 10'd720)
        data <= WHITE;
    else if(x > 10'd720 && x <= 10'd800)
        data <= GRAY;
    else
        data <= BLACK;
            

endmodule

驱动模块：

module tft_lcd
(
    input       wire            sys_clk,//33.3Mhz,65HZ
    input       wire            rst,
    input       wire    [15:0]  data,
    
    output      wire    [15:0]  RGB,
    output      wire            Vsync_t,
    output      wire            Hsync_t,
    output      wire            DE,
    output      wire     [9:0]   x,
    output      wire     [9:0]   y
);

assign RGB = data;

//parameter define
parameter Hsync    =   11'd1    ,   //琛屽悓姝
          H_BACK    =   11'd46   ,   //琛屾椂搴忓悗娌
          H_VALID   =   11'd800  ,   //琛屾湁鏁堟暟鎹
          H_FRONT   =   11'd210  ,   //琛屾椂搴忓墠娌
          H_TOTAL   =   11'd1057 ;   //琛屾壂鎻忓懆鏈

parameter Vsync    =   11'd1    ,   //鍦哄悓姝
          V_BACK    =   11'd23   ,   //鍦烘椂搴忓悗娌
          V_VALID   =   11'd480  ,   //鍦烘湁鏁堟暟鎹
          V_FRONT   =   11'd22   ,   //鍦烘椂搴忓墠娌
          V_TOTAL   =   11'd526  ;   //鍦烘壂鎻忓懆鏈

reg [10:0]  cnt_tft;
reg [10:0]  cnt_tft_v;
wire        rgb_valid;

assign DE = (cnt_tft >= Hsync + H_BACK - 1'd1 
            && cnt_tft <= Hsync + H_BACK + H_VALID - 1'd1
            && cnt_tft_v >= Vsync + V_BACK - 1'd1
            && cnt_tft_v <= Vsync + V_BACK + V_VALID - 1'd1)?1'd1:1'd0;
            
assign rgb_valid = (cnt_tft >= Hsync + H_BACK - 2'd2 
                    && cnt_tft <= Hsync + H_BACK + H_VALID - 1'd1
                    && cnt_tft_v >= Vsync + V_BACK - 1'd1
                    && cnt_tft_v <= Vsync + V_BACK + V_VALID - 1'd1)?1'd1:1'd0;
            
assign Hsync_t = (cnt_tft <= Hsync - 1'D1)?1'd1:1'd0;
assign Vsync_t = (cnt_tft_v <= Vsync - 1'D1)?1'd1:1'd0;

assign x = (rgb_valid == 1'd1)?cnt_tft + 2'd2 - Hsync - H_BACK:1'd0;           
assign y = (rgb_valid == 1'd1)?cnt_tft_v + 1'd1 - Vsync - V_BACK:1'd0;

always@(posedge sys_clk or negedge rst)
    if(rst == 1'd0)
        cnt_tft <= 1'd0;
    else if(cnt_tft == H_TOTAL - 1'd1)
        cnt_tft <= 1'd0;
    else
        cnt_tft <= cnt_tft + 1'd1;
        
always@(posedge sys_clk or negedge rst)
    if(rst == 1'd0)
        cnt_tft_v <= 1'd0;
    else if(cnt_tft == H_TOTAL - 1'd1 && cnt_tft_v == V_TOTAL - 1'd1)
        cnt_tft_v <= 1'd0;
    else if(cnt_tft == H_TOTAL - 1'd1)
        cnt_tft_v <= cnt_tft_v + 1'd1;

endmodule

顶层模块：

module tft_top
(
    input       wire                sys_clk,//33.3Mhz,65HZ
    input       wire                rst,
    
    output      wire    [15:0]  RGB,
    output      wire            Vsync,
    output      wire            Hsync,
    output      wire            DE
);

wire     [9:0]      x;
wire     [9:0]      y;
wire     [15:0]     data;

tft_data tft_data_inst
(
    .sys_clk(sys_clk),//33.3Mhz,65HZ
    .rst(rst),
    .x(x),
    .y(y),
    
    .data(data)
);

tft_lcd tft_lcd_inst
(
    .sys_clk(sys_clk),//33.3Mhz,65HZ
    .rst(rst),
    .data(data),
    
    .RGB(RGB),
    .Vsync_t(Vsync),
    .Hsync_t(Hsync),
    .DE(DE),
    .x(x),
    .y(y)
);

endmodule