CACHE 函数 for ti

1.CACHE_clean:

Function       void CACHE_clean(
      CACHE_Region region, 
      void *addr, 
      Uint32 wordCnt
);
Arguments       region Specifies which cache region to clean; must be one of the following:

CACHE_L2  

CACHE_L2ALL 
addr               Beginning address of range to clean; word aligned
wordCnt         Number of 4-byte words to clean
Return Value         none 
Description

Cleans a range of L2 cache. All lines within the range defined by addr and wordCnt are cleaned out of L2. If CACHE_L2ALL is specified, then all of L2 is cleaned, addr and wordCnt are ignored. A clean operation involves writing back all dirty cache lines and then invalidating those lines. This routine waits until the operation completes before returning.
Note: This function does nothing on devices without L2 cache.
Example

If you want to clean a 4K-byte range that starts at 0x80000000 out of L2, use:CACHE_clean(CACHE_L2,(void*)0x80000000,0x00000400);

If you want to clean all lines out of L2 use:CACHE_clean(CACHE_L2ALL, (void*)0x00000000,0x00000000);

2.CACHE_enableCaching

Function         Void CACHE_enableCaching(Uint32 block);
Arguments       block        Specifies a block of external memory to enable caching for; must one of the following:

?CACHE_CE33 -(0xB3000000 to 0xB3FFFFFF)

?CACHE_CE32 -(0xB2000000 to 0xB2FFFFFF)

?CACHE_CE31 -(0xB1000000 to 0xB1FFFFFF)

?CACHE_CE30 -(0xB0000000 to 0xB0FFFFFF)

?CACHE_CE23 -(0xA3000000 to 0xA3FFFFFF)

?CACHE_CE22 -(0xA2000000 to 0xA2FFFFFF)

?CACHE_CE21 -(0xA1000000 to 0xA1FFFFFF)

?CACHE_CE20 -(0xA0000000 to 0xA0FFFFFF)

?CACHE_CE13 -(0x93000000 to 0x93FFFFFF)

?CACHE_CE12 -(0x92000000 to 0x92FFFFFF)

?CACHE_CE11 -(0x91000000 to 0x91FFFFFF)

?CACHE_CE10 -(0x90000000 to 0x90FFFFFF)

?CACHE_CE03 -(0x83000000 to 0x83FFFFFF)

?CACHE_CE02 -(0x82000000 to 0x82FFFFFF)

?CACHE_CE01 -(0x81000000 to 0x81FFFFFF)

?CACHE_CE00 -(0x80000000 to 0x80FFFFFF)
Return Value         none 
Description            Enables caching for the specified block of memory. This is accomplished by setting the CE bit in the appropriate memory attribute register (MAR). By default, caching is disabled for all memory spaces.

Note: This function does nothing on devices without L2 cache.
Example To enable caching for the range of memory from 0x80000000 to 0x80FFFFFF use:CACHE_enableCaching(CACHE_CE00);

3.CACHE_flush

Function void CACHE_flush(
    CACHE_Region region,
    void *addr,
    Uint32 wordCnt
);
Arguments     region     Specifies which cache region to flush from; must be one of the following:

?CACHE_L2  

?CACHE_L2ALL

?CACHE_L1D 
addr                                  Beginning address of range to flush; word aligned
wordCnt                            Number of 4-byte words to flush
Return Value      none        Number of 4-byte words to flush
Description                       Flushes a range of L2 cache. All lines within the range defined by addr and wordCnt are flushed out of L2. If CACHE_L2ALL is specified, then all of L2 is flushed; addr and wordCnt are ignored. A flush operation involves writing back all dirty cache lines, but the lines are not invalidated. This routine waits until the operation completes before returning.
Note: This function does nothing on devices without L2 cache.
Example

If you want to flush a 4K-byte range that starts at 0x80000000 out of L2, use:CACHE_flush(CACHE_L2,(void*)0x80000000,0x00000400);

If you want to flush all lines out of L2, use:CACHE_flush(CACHE_L2ALL,(void*)0x00000000,0x00000000);

4.CACHE_getL2SramSize

Function Uint32 CACHE_getL2SramSize();
Arguments     none 
Return Value   size     Returns number of bytes of on-chip SRAM
Description This function returns the current size of L2 that is configured as SRAM.

Note: This function does nothing on devices without L2 cache.
Example SramSize = CACHE_getL2SramSize();

5.CACHE_reset

Function void CACHE_reset();
Arguments none 
Return Value none 
Description Resets cache to power-on default. Devices with L2 Cache:

?All MAR bits are clearedDevices without L2 Cache:

?PCC field of CSR set to zero (mapped)

Note: If you reset the cache, any dirty data will be lost. If you want to preserve this data, flush it out first.
Example CACHE_reset();

6.CACHE_setL2Mode

Function     CACHE_L2Mode CACHE_setL2Mode(
   CACHE_L2Mode newMode
);
Arguments        newMode      New L2 cache mode; must be one of the following:

?CACHE_0KSRAM

?CACHE_16KSRAM

?CACHE_32KSRAM

?CACHE_48KSRAM

?CACHE_64KSRAM

?CACHE_0KCACHE

?CACHE_16KCACHE

?CACHE_32KCACHE

?CACHE_48KCACHE

?CACHE_64KCACHE
Return Value      OldMode Returns old cache mode; will be one of the following:

?CACHE_0KSRAM

?CACHE_16KSRAM

?CACHE_32KSRAM

?CACHE_48KSRAM

?CACHE_64KSRAM

?CACHE_0KCACHE

?CACHE_16KCACHE

?CACHE_32KCACHE

?CACHE_48KCACHE

?CACHE_64KCACHE
Description      Sets the mode of the L2 cache. There are three conditions that may occur as a result of changing cache modes:1. A decrease in cache size2. An increase in cache size3. No change in cache sizeIf the cache size decreases, all of L2 is flushed; then the mode is changed. If the cache size increases, the part of SRAM that is about to be turned into cache is flushed out of L1; then the mode is changed. Nothing happens when there is no change.Increasing cache size means that some of the SRAM is lost. If you have data in SRAM that you do not want lost, you must preserve it yourself before changing cache modes.Some of the cache modes are identical.

For example, on the 6211 there are 64K-bytes of L2; hence, CACHE_16KSRAM is equivalent to CACHE_48KCACHE. However, if the L2 size changes on a future device, this will not be the case.Note: This function does nothing on devices without L2 cache.
Example CACHE_L2Mode OldMode;OldMode = CACHE_setL2Mode(CACHE_32KCACHE);