【HDLBits刷题】Shift4.

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

areset: Resets shift register to zero.
load: Loads shift register with data[3:0] instead of shifting.
ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.

Module Declaration

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 

错误的代码：

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 

    always @(posedge clk or posedge areset)
        begin
            if(areset) begin
                q =0;
            end
            else begin
                q[2:0] = q[3:1];
                q[3] = 0;
            end
            if(load) begin
                q=data;
            end
        end
endmodule

这段代码报综合错误：
Error (10200): Verilog HDL Conditional Statement error at top_module.v(18): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct File: /home/h/work/hdlbits.15039432/top_module.v Line: 18

这里的问题是在always中areset和load都对q进行了操作，但是作为两个并行的条件分支，可能同时发生。

正确的代码：

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q
);

    always @(posedge clk or posedge areset) begin
        if (areset) begin
            q <= 4'b0000;
        end else if (load) begin
            q <= data;
        end else if (ena) begin
            q <= {1'b0,q[3:1],};
        end
    end

endmodule

写成一个if条件的不同分支的形式。