HDLbits答案更新系列16（3.2.5 Finite State Machines 3.2.5.20 Sequence recognition等）

 

目录

前言

3.2.5 Finite State Machines

3.2.5.20 Sequence recognition（Fsm hdlc）

3.2.5.21 Q8:Design a Mealy FSM（Exams/ece241 2013 q8）

3.2.5.22 Q5a:Serial two's complementer（Moore FSM）（Exams/ece241 2014 q5a）

3.2.5.23 Q5b:Serial two's complementer（Mealy FSM）（Exams/ece241 2014 q5b）

结语

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---

前言

今天继续更新几道题目。

3.2.5 Finite State Machines

3.2.5.20 Sequence recognition（Fsm hdlc）

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter S1 = 4'd1, S2 = 4'd2, S3 = 4'd3, S4 = 4'd4, S5 = 4'd5;
    parameter S6 = 4'd6, S7 = 4'd7, DISC = 4'd8, ERR = 4'd9, FLAG = 4'd10;
    
    reg	[3:0]	current_state;
    reg [3:0]	next_state;
    
    always@(posedge clk)begin
        if(reset == 1'b1)begin
            current_state <= S1;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            S1:begin
                next_state = in ? S2 : S1;
            end
            S2:begin
                next_state = in ? S3 : S1;
            end
            S3:begin
                next_state = in ? S4 : S1;
            end
            S4:begin
                next_state = in ? S5 : S1;
            end
            S5:begin
                next_state = in ? S6 : S1;
            end
            S6:begin
                next_state = in ? S7 : DISC;
            end
            S7:begin
                next_state = in ? ERR : FLAG;
            end
            DISC:begin
                next_state = in ? S2 : S1;
            end
            ERR:begin
                next_state = in ? ERR : S1;
            end
            FLAG:begin
                next_state = in ? S2 : S1;
            end
            default:begin
                next_state = S1;
            end
        endcase
    end
    
    assign disc = (current_state == DISC);
    assign err = (current_state == ERR);
    assign flag = (current_state == FLAG);

endmodule

题目中说in为01111110时，这个标志表示帧边界（即6个连续的1），如果in为0111110，那么将进入丢弃状态（即5个1后面来了个一个0），如果in中包含7个以上的1，则进入错误状态。熟悉了题意，这道题目应该没什么难度。

3.2.5.21 Q8:Design a Mealy FSM（Exams/ece241 2013 q8）

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter S0 = 2'd0, S1 = 2'd1, S2 = 2'd2;
    reg [1:0]	current_state;
    reg [1:0]	next_state;
    
    always@(posedge clk or negedge aresetn)begin
        if(aresetn == 1'b0)begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            S0:begin
                next_state = x ? S1 : S0;
            end
            S1:begin
                next_state = x ? S1 : S2;
            end
            S2:begin
                next_state = x ? S1 : S0;
            end
            default:begin
                next_state = S0;
            end
        endcase
    end
    
    always@(*)begin
        case(current_state)
            S0:begin
                z = 1'b0;
            end
            S1:begin
                z = 1'b0;
            end
            S2:begin
                z = x;
            end
        endcase
    end

    //assign z = ((current_state == S2) && (x == 1'b1)) ? 1'b1 : 1'b0;

endmodule

这道题目就是一道简单地mealy型状态机序列检测的问题，检测“101”序列。注意，题目中要求重叠检测，比如“10101”，z应该两次拉高，其他应该就没什么难度了。

3.2.5.22 Q5a:Serial two's complementer（Moore FSM）（Exams/ece241 2014 q5a）

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    
    parameter A = 2'd0, B = 2'd1, C = 2'd2;
    reg	[1:0]	current_state;
    reg	[1:0]	next_state;
    
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            current_state <= A;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            A:begin
                next_state = x ? B : A;
            end
            B:begin
                next_state = x ? C : B;
            end
            C:begin
                next_state = x ? C : B;
            end
            default:begin
                next_state = A;
            end
        endcase
    end
    
    assign z = current_state == B;

endmodule

这道题目是要求2的补码，这里作者假设了我们输入的都是负数，不用管符号位的问题。大家根据时序图应该可以完成。注意，这道题目的输入是从LSB（最低有效位）开始的，比如我们要转换为补码的数据为100101，那么x的输入顺序应该为101001。博主在完成这道题目的时候，由于作者没有给隐含条件（输入都是负数），所以有点懵，但是看了下面一道题目的状态转移图，豁然开朗，建议遇到困难的同学可以先看一看下面这道题目。

更新：同学们可以参考评论区许加运同学的评论，可以帮大家更快理清思路。

3.2.5.23 Q5b:Serial two's complementer（Mealy FSM）（Exams/ece241 2014 q5b）

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    parameter A = 1'b0, B = 1'b1;
    reg	current_state;
    reg	next_state;
    
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            current_state <= A;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            A:begin
                next_state = x ? B : A;
            end
            B:begin
                next_state = B;
            end
        endcase
    end
    
    assign z = (current_state == A && x == 1'b1 || current_state == B && x == 1'b0);
    
endmodule

这道题目和上一道题目相同，只不过作者要求用mealy型状态机完成，状态转移图已经给出了，难度系数瞬间降了好多，大家可以根据这道题目完成上一道题目。

结语

今天先更新这几道题目吧，祝大家周末愉快~~~如果有什么有问题的地方欢迎随时留言。

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