RISC计算机组成原理,计算机组成原理与接口技术课件 CHAPTER 23 PENTIUM AND RISC PROCESSORS 589.pdf...

Dec Hex Bin

23 17

ORG ; TWENTY-THREE

PENTIUM

AND RISC

PROCESSORS

The x86 PC

Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.

By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458

OBJECTIVES

this chapter enables the student to:

• List the design enhancements of the x86

microprocessors from 80486 to Pentium® 4.

• Discuss the advantages of the 5-stage pipeline

over the 2-stage pipeline.

• Explain how the burst cycle is used to increase

memory cycle times for read/write operations.

• Compare the cache sizes of x86 processors

from 486 to Pentium® 4.

• List three ways that designers can increase the

processing power of a CPU.

The x86 PC

Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.

By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458

OBJECTIVES (cont)

this chapter enables the student to:

• List design enhancements of the Pentium® over

previous-generation x86 microprocessors.

• Describe the impact on performance of the

®

64-bit data bus of the Pentium .

• Describe superscalar architecture and Harvard

®

architecture and their use in the Pentium .

• List the unique features of RISC architecture

compared to CISC and describe the impact on

processing speed and program de