html5264文件,SAA5264 Datasheet(数据表) 5 Page - NXP Semiconductors

2000 Jan 27

5

Philips Semiconductors

Preliminary specification

10 and 1 page intelligent teletext decoders

SAA5264; SAA5265

PINNING

SYMBOL

PIN

TYPE

DESCRIPTION

Port 2: 8-bit programmable bidirectional port with alternative functions

P2.0/PWM

1

I/O

output for 14-bit high precision Pulse Width Modulator (PWM)

P2.1/PWM0

2

I/O

outputs for 6-bit PWMs 0 to 6

P2.2/PWM1

3

I/O

P2.3/PWM2

4

I/O

P2.4/PWM3

5

I/O

P2.5/PWM4

6

I/O

P2.6/PWM5

7

I/O

P2.7/PWM6

8

I/O

Port 3: 8-bit programmable bidirectional port with alternative functions

P3.0/ADC0

9

I/O

inputs for the software Analog-to-Digital-Converter (ADC) facility

P3.1/ADC1

10

I/O

P3.2/ADC2

11

I/O

P3.3/ADC3

12

I/O

P3.4/PWM7

30

I/O

output for 6-bit PWM7

VSSC

13

−

core ground

Port 0: 8-bit programmable bidirectional port

SCL(NVRAM)

14

I

I2C-bus Serial Clock input to Non-Volatile RAM

SDA(NVRAM)

15

I/O

I2C-bus Serial Data input/output (Non-Volatile RAM)

P0.2

16

I/O

input/output for general use

P0.3

17

I/O

input/output for general use

P0.4

18

I/O

input/output for general use

P0.5

19

I/O

8 mA current sinking capability for direct drive of Light Emitting Diodes (LEDs)

P0.6

20

I/O

P0.7

21

I/O

input/output for general use

VSSA

22

−

analog ground

CVBS0

23

I

Composite Video Baseband Signal (CVBS) input; a positive-going 1 V

(peak-to-peak) input is required; connected via a 100 nF capacitor

CVBS1

24

I

SYNC_FILTER

25

I

sync-pulse-filter input for CVBS; this pin should be connected to VSSAvia a

100 nF capacitor

IREF

26

I

reference current input for analog circuits; for correct operation a 24 k

Ω resistor

should be connected to VSSA

FRAME

27

O

Frame de-interlace output synchronized with the VSYNC pulse to produce a

non-interlaced display by adjustment of the vertical deflection circuits

TEST

28

I

not available; connect this pin to VSSA

COR

29

O

contrast reduction: open-drain, active LOW output which allows selective contrast

reduction of the TV picture to enhance a mixed mode display

30

I/O

P3.4/PWM7 (described above)

VDDA

31

−

analog supply voltage (3.3 V)

B

32

O

Blue colour information pixel rate output