sedemo_variable_entity_replication
Design Description
danniel
sedemo_variable_entity_replication: Design
Description
by danniel
Published 19-Feb-2011 13:25:31
Copyright © 2011
For Internal Distribution Only
Table of Contents
.......................................................................................................................................................
1
2. Root
System............................................................................................................................................................
2
2
2.1.1.
Parameters...................................................................................................................................
2
2.1.2. Block Execution
Order..............................................................................................................
2
3.
Subsystems..............................................................................................................................................................
5
5
3.1.1.
Interface......................................................................................................................................
5
3.1.1.1. Input
Signals.................................................................................................................
5
3.1.1.2. Output
Signals...............................................................................................................
6
3.1.2.
Blocks...........................................................................................................................................
6
3.1.2.1.
Parameters.....................................................................................................................
6
3.1.2.1.1.
"Bias"
(Bias)....................................................................................................
6
3.1.2.1.2.
"Din"
(Inport)..................................................................................................
6
3.1.2.1.3.
"Din1"
(Inport)................................................................................................
7
3.1.2.1.4.
"le"
(Outport)...................................................................................................
7
3.1.2.1.5.
"le p1"
(Outport).............................................................................................
7
3.1.3. Block
Execution
Order..............................................................................................................
8
4. Requirements
Traceability................................................................................................................................
9
5. System Model
Configuration..........................................................................................................................
10
6.
Glossary................................................................................................................................................................
32
7. About this
Report................................................................................................................................................
33
33
7.2. Root System
Description......................................................................................................................
33
7.3. Subsystem
Descriptions........................................................................................................................
34
7.4. State Chart
Descriptions.......................................................................................................................
34
List of Tables
5
3-2.
Din1<1>................................................................................................................................................................
5
3-3. Relational
Operator<1>.....................................................................................................................................
6
3-4.
Bias<1>................................................................................................................................................................
6
3-5.
"Bias"
Parameters...............................................................................................................................................
6
3-6.
"Din"
Parameters................................................................................................................................................
6
3-7.
"Din1"
Parameters..............................................................................................................................................
7
3-8.
"Relational Operator"
Parameters...................................................................................................................
7
4-1.
sedemo_variable_entity_replication Version
Information........................................................................
9
5-1.
sedemo_variable_entity_replication Configuration Set
.........................................................................
10
5-14. HDL Coder
....................................................................................................................................................
26
List of Figures
2
3-1.
sedemo_variable_entity_replication/Compare/__fcn_ss__......................................................................
5
Chapter 1. Model Version
Version: 1.35
Last modified: Wed Jul 7 21:27:40 2010
Checksum: 3411420256 1819692349 166368803 1285611164
Chapter 2. Root System
Figure 2-1.
sedemo_variable_entity_replication
2.1. Blocks
2.1.1. Parameters
2.1.2. Block Execution Order
1. actuator (Actuator)
2. pmioport (PMIOPort)
3. __Signal Scope__ (PMComponent)
4. actuator (Actuator)
5. pmioport (PMIOPort)
6. __Output Switch__ (PMComponent)
7. IN (PMIOPort)
8. OUT1 (PMIOPort)
9. OUT2 (PMIOPort)
10. actuator (Actuator)
11. pmioport (PMIOPort)
12. __Signal Scope__ (PMComponent)
13. ___cec_sfun_d2s_3__ (S-Function)
14. TmpAtomicSubsysAt___cec_sfun_d2s_3__Outport1
15. ___cec_sfun_d2s_1__ (S-Function)
16. TmpAtomicSubsysAt___cec_sfun_d2s_1__Outport1
17. __fcn_ss__
18. c_Din (Constant)
19. c_Din1 (Constant)
20. sensor (Sensor)
21. pmioport (PMIOPort)
22. actuator (Actuator)
23. pmioport (PMIOPort)
24. actuator (Actuator)
25. pmioport (PMIOPort)
26. __Signal-Based Event to Function-Call Event__
(PMComponent)
27. sensor (Sensor)
28. pmioport (PMIOPort)
29. actuator (Actuator)
30. pmioport (PMIOPort)
31. actuator (Actuator)
32. pmioport (PMIOPort)
33. __Signal-Based Event to Function-Call Event__
(PMComponent)
34. sensor (Sensor)
35. pmioport (PMIOPort)
36. actuator (Actuator)
37. pmioport (PMIOPort)
38. __Entity Departure Counter__ (PMComponent)
39. IN (PMIOPort)
40. OUT (PMIOPort)
41. sensor (Sensor)
42. pmioport (PMIOPort)
43. __Get Attribute__ (PMComponent)
44. IN (PMIOPort)
45. OUT (PMIOPort)
46. actuator (Actuator)
47. pmioport (PMIOPort)
48. __Signal Scope__ (PMComponent)
49. sensor (Sensor)
50. pmioport (PMIOPort)
51. __Entity Sink__ (PMComponent)
52. IN (PMIOPort)
53. actuator (Actuator)
54. pmioport (PMIOPort)
55. __Signal Scope__ (PMComponent)
56. actuator (Actuator)
57. pmioport (PMIOPort)
58. __Set Attribute__ (PMComponent)
59. IN (PMIOPort)
60. OUT (PMIOPort)
61. S-Function (S-Function)
62. TmpAtomicSubsysAtS-FunctionOutport1
63. __Entity Sink__ (PMComponent)
64. IN (PMIOPort)
65. __Infinite Server__ (PMComponent)
66. IN (PMIOPort)
67. OUT (PMIOPort)
68. __Path Combiner__ (PMComponent)
69. IN1 (PMIOPort)
70. IN2 (PMIOPort)
71. OUT (PMIOPort)
72. __Replicate__ (PMComponent)
73. IN (PMIOPort)
74. OUT1 (PMIOPort)
75. OUT2 (PMIOPort)
76. __Time-Based Entity Generator__ (PMComponent)
77. OUT (PMIOPort)
78. ___ed_sfun_s2d_1__ (S-Function)
79. ___ed_sfun_s2d_2__ (S-Function)
80. ___prop_helper_sfun___ (S-Function)
81. ___prop_sfun_ (S-Function)
82. ___cec_sfun_d2s_2__ (S-Function)
83. TmpAtomicSubsysAt___cec_sfun_d2s_2__Outport1
84. ___vs_sfun___ (S-Function)
85. zzzzzzz-last_MR-S-Function (S-Function)
Chapter 3. Subsystems
3.1. __fcn_ss__
Checksum: 689656377 1461312665 800447132 2823402373
Figure 3-1.
sedemo_variable_entity_replication/Compare/__fcn_ss__
3.1.1. Interface
3.1.1.1. Input Signals
The following tables describe external signals used to compute
the subsystem's inputs.The name of the input signal is the name of
the input port that accepts the signal. The number in angle
brackets is the number of the input port. A dimension of [1 1]
indicates a scalar signal.
Table 3-1.
Din<1>
Description:
Data Type: double
Width: 1
Dimensions: [1 1 ]
Table 3-2.
Din1<1>
Description:
Data Type: double
Width: 1
Dimensions: [1 1 ]
3.1.1.2. Output Signals
The following tables describe the signals output by the this
system. The name of the output signal is the name of the signal's
parent block, i.e., the block that computes the signal. The number
in angle brackets is the number of the port that emits the
signal.
Table 3-3. Relational
Operator<1>
Description:
Data Type: double
Width: 1
Dimensions: [1 1 ]
Table 3-4.
Bias<1>
Description:
Data Type: double
Width: 1
Dimensions: [1 1 ]
3.1.2. Blocks
3.1.2.1. Parameters
3.1.2.1.1.
"Bias" (Bias)
Table 3-5.
"Bias" Parameters
Parameter
Value
Bias
1
3.1.2.1.2.
"Din" (Inport)
Table 3-6.
"Din" Parameters
Parameter
Value
Execute subsystem upon signal-based events
on
Type of signal-based event
Sample time hit
Type of change in signal value
Rising
Resolve simultaneous signal updates according to event
priority
off
3.1.2.1.3.
"Din1" (Inport)
Table 3-7.
"Din1" Parameters
Parameter
Value
Execute subsystem upon signal-based events
on
Type of signal-based event
Sample time hit
Type of change in signal value
Rising
Resolve simultaneous signal updates according to event
priority
off
3.1.2.1.4.
"le" (Outport)
3.1.2.1.5. "le
p1" (Outport)
3.1.2.1.6. "Relational
Operator" (RelationalOperator)
Table 3-8. "Relational
Operator" Parameters
Parameter
Value
Relational operator
<=
Require all inputs to have the same data type
off
Output data type
float('double')
Enable zero-crossing detection
on
Sample time (-1 for inherited)
-1
3.1.2.1.7. "Subsystem
Configuration" (TriggerPort)
3.1.3. Block Execution Order
1. Relational Operator (RelationalOperator)
2. ___mr_sfun_s2d_4__ (S-Function)
3. Bias (Bias)
4. ___mr_sfun_s2d_8__ (S-Function)
5. ___mr_sfun_s2d_1__ (S-Function)
Chapter 4. Requirements
Traceability
4.1. Model Information for
"sedemo_variable_entity_replication"
Table 4-1.
sedemo_variable_entity_replication Version Information
ModelVersion
1.35
ConfigurationManager
None
Created
Wed Apr 4 17:36:20 2007
Creator
The MathWorks Inc.
LastModifiedDate
Wed Jul 7 21:27:40 2010
LastModifiedBy
4.2. Document Summary for
"sedemo_variable_entity_replication"
.
Chapter 5. System Model
Configuration
Table 5-1.
sedemo_variable_entity_replication Configuration Set
Property
Value
Name
Solver
Description
Components
StartTime
0
StopTime
10.0
AbsTol
auto
FixedStep
auto
InitialStep
auto
MaxNumMinSteps
-1
MaxOrder
5
ZcThreshold
auto
ConsecutiveZCsStepRelTol
10*128*eps
MaxConsecutiveZCs
1000
ExtrapolationOrder
4
NumberNewtonIterations
1
MaxStep
inf
MinStep
auto
MaxConsecutiveMinStep
1
RelTol
1e-3
SolverMode
Auto
Solver
VariableStepDiscrete
SolverName
VariableStepDiscrete
SolverType
Variable-step
SolverJacobianMethodControl
auto
ShapePreserveControl
DisableAll
ZeroCrossControl
UseLocalSettings
ZeroCrossAlgorithm
Nonadaptive
SolverResetMethod
Fast
PositivePriorityOrder
off
AutoInsertRateTranBlk
off
SampleTimeConstraint
Unconstrained
InsertRTBMode
Whenever possible
SampleTimeProperty
Property
Value
Name
Data Import/Export
Description
Components
Decimation
1
ExternalInput
[t, u]
FinalStateName
xFinal
InitialState
xInitial
LimitDataPoints
on
MaxDataPoints
1000
LoadExternalInput
off
LoadInitialState
off
SaveFinalState
off
SaveCompleteFinalSimState
off
SaveFormat
Array
SignalLoggingSaveFormat
LegacyTimeseries
SaveOutput
off
SaveState
off
SignalLogging
off
DSMLogging
on
InspectSignalLogs
off
SaveTime
off
ReturnWorkspaceOutputs
off
StateSaveName
xout
TimeSaveName
tout
OutputSaveName
yout
SignalLoggingName
logsout
DSMLoggingName
dsmout
OutputOption
RefineOutputTimes
OutputTimes
[]
ReturnWorkspaceOutputsName
out
Refine
1
Property
Value
Name
Optimization
Description
Components
BlockReduction
on
BooleanDataType
on
ConditionallyExecuteInputs
on
InlineParams
off
UseIntDivNetSlope
off
UseSpecifiedMinMax
off
InlineInvariantSignals
off
OptimizeBlockIOStorage
on
BufferReuse
on
EnhancedBackFolding
off
StrengthReduction
off
AdvancedOptControl
EnforceIntegerDowncast
on
ExpressionFolding
on
BooleansAsBitfields
off
BitfieldContainerType
uint_T
EnableMemcpy
on
MemcpyThreshold
64
PassReuseOutputArgsAs
Structure reference
PassReuseOutputArgsThreshold
12
FoldNonRolledExpr
on
LocalBlockOutputs
on
RollThreshold
5
SystemCodeInlineAuto
off
StateBitsets
off
DataBitsets
off
UseTempVars
off
ZeroExternalMemoryAtStartup
on
ZeroInternalMemoryAtStartup
on
InitFltsAndDblsToZero
on
NoFixptDivByZeroProtection
off
EfficientFloat2IntCast
off
EfficientMapNaN2IntZero
on
OptimizeModelRefInitCode
off
LifeSpan
inf
EvaledLifeSpan
Inf
MaxStackSize
Inherit from target
BufferReusableBoundary
on
SimCompilerOptimization
Off
AccelVerboseBuild
off
Property
Value
Name
Diagnostics
Description
Components
RTPrefix
error
ConsistencyChecking
none
ArrayBoundsChecking
none
SignalInfNanChecking
none
SignalRangeChecking
none
ReadBeforeWriteMsg
UseLocalSettings
WriteAfterWriteMsg
UseLocalSettings
WriteAfterReadMsg
UseLocalSettings
AlgebraicLoopMsg
error
ArtificialAlgebraicLoopMsg
warning
SaveWithDisabledLinksMsg
warning
SaveWithParameterizedLinksMsg
warning
CheckSSInitialOutputMsg
on
CheckExecutionContextPreStartOutputMsg
off
CheckExecutionContextRuntimeOutputMsg
off
SignalResolutionControl
UseLocalSettings
BlockPriorityViolationMsg
warning
MinStepSizeMsg
warning
TimeAdjustmentMsg
none
MaxConsecutiveZCsMsg
error
MaskedZcDiagnostic
warning
IgnoredZcDiagnostic
warning
SolverPrmCheckMsg
none
InheritedTsInSrcMsg
warning
DiscreteInheritContinuousMsg
warning
MultiTaskDSMMsg
error
MultiTaskCondExecSysMsg
error
MultiTaskRateTransMsg
error
SingleTaskRateTransMsg
none
TasksWithSamePriorityMsg
warning
SigSpecEnsureSampleTimeMsg
warning
CheckMatrixSingularityMsg
none
IntegerOverflowMsg
warning
Int32ToFloatConvMsg
warning
ParameterDowncastMsg
error
ParameterOverflowMsg
error
ParameterUnderflowMsg
none
ParameterPrecisionLossMsg
warning
ParameterTunabilityLossMsg
warning
FixptConstUnderflowMsg
none
FixptConstOverflowMsg
none
FixptConstPrecisionLossMsg
none
UnderSpecifiedDataTypeMsg
none
UnnecessaryDatatypeConvMsg
none
VectorMatrixConversionMsg
none
InvalidFcnCallConnMsg
error
FcnCallInpInsideContextMsg
Use local settings
SignalLabelMismatchMsg
none
UnconnectedInputMsg
warning
UnconnectedOutputMsg
warning
UnconnectedLineMsg
warning
SFcnCompatibilityMsg
none
UniqueDataStoreMsg
none
BusObjectLabelMismatch
warning
RootOutportRequireBusObject
warning
AssertControl
UseLocalSettings
Echo
EnableOverflowDetection
off
ModelReferenceIOMsg
none
ModelReferenceVersionMismatchMessage
none
ModelReferenceIOMismatchMessage
none
ModelReferenceCSMismatchMessage
none
ModelReferenceSimTargetVerbose
off
UnknownTsInhSupMsg
warning
ModelReferenceDataLoggingMessage
warning
ModelReferenceSymbolNameMessage
warning
ModelReferenceExtraNoncontSigs
error
StateNameClashWarn
warning
SimStateInterfaceChecksumMismatchMsg
warning
InitInArrayFormatMsg
warning
StrictBusMsg
Warning
BusNameAdapt
WarnAndRepair
NonBusSignalsTreatedAsBus
none
LoggingUnavailableSignals
error
SFUnusedDataAndEventsDiag
warning
SFUnexpectedBacktrackingDiag
warning
SFInvalidInputDataAccessInChartInitDiag
warning
SFNoUnconditionalDefaultTransitionDiag
warning
SFTransitionOutsideNaturalParentDiag
warning
Property
Value
Name
Hardware
Implementation
Description
Components
ProdBitPerChar
8
ProdBitPerShort
16
ProdBitPerInt
32
ProdBitPerLong
32
ProdBitPerFloat
32
ProdBitPerDouble
64
ProdBitPerPointer
32
ProdLargestAtomicInteger
Char
ProdLargestAtomicFloat
None
ProdIntDivRoundTo
Undefined
ProdEndianess
Unspecified
ProdWordSize
32
ProdShiftRightIntArith
on
ProdHWDeviceType
32-bit Generic
TargetBitPerChar
8
TargetBitPerShort
16
TargetBitPerInt
32
TargetBitPerLong
32
TargetBitPerFloat
32
TargetBitPerDouble
64
TargetBitPerPointer
32
TargetLargestAtomicInteger
Char
TargetLargestAtomicFloat
None
TargetShiftRightIntArith
on
TargetIntDivRoundTo
Undefined
TargetEndianess
Unspecified
TargetWordSize
32
TargetTypeEmulationWarnSuppressLevel
0
TargetPreprocMaxBitsSint
32
TargetPreprocMaxBitsUint
32
TargetHWDeviceType
Specified
TargetUnknown
off
ProdEqTarget
on
Property
Value
Name
Model Referencing
Description
Components
UpdateModelReferenceTargets
IfOutOfDateOrStructuralChange
CheckModelReferenceTargetMessage
error
EnableParallelModelReferenceBuilds
off
ParallelModelReferenceErrorOnInvalidPool
on
ParallelModelReferenceMATLABWorkerInit
None
ModelReferenceNumInstancesAllowed
Multi
PropagateVarSize
Infer from blocks in
model
ModelDependencies
ModelReferencePassRootInputsByReference
on
ModelReferenceMinAlgLoopOccurrences
off
PropagateSignalLabelsOutOfModel
off
SupportModelReferenceSimTargetCustomCode
off
Property
Value
Name
Simulation Target
Description
Components
SimCustomSourceCode
SimCustomHeaderCode
SimCustomInitializer
SimCustomTerminator
SimReservedNameArray
SimUserSources
SimUserIncludeDirs
SimUserLibraries
SFSimEnableDebug
on
SFSimOverflowDetection
on
SFSimEcho
on
SimBlas
on
SimCtrlC
on
SimExtrinsic
on
SimIntegrity
on
SimUseLocalCustomCode
off
SimParseCustomCode
on
SimBuildMode
sf_incremental_build
SimDataInitializer
Property
Value
Name
Real-Time Workshop
SystemTargetFile
grt.tlc
TLCOptions
CodeGenDirectory
GenCodeOnly
off
MakeCommand
make_rtw
GenerateMakefile
on
TemplateMakefile
grt_default_tmf
PostCodeGenCommand
Description
GenerateReport
off
SaveLog
off
RTWVerbose
on
RetainRTWFile
off
ProfileTLC
off
TLCDebug
off
TLCCoverage
off
TLCAssert
off
ProcessScriptMode
Default
ConfigurationMode
Optimized
ProcessScript
ConfigurationScript
ConfigAtBuild
off
RTWUseLocalCustomCode
off
RTWUseSimCustomCode
off
CustomSourceCode
CustomHeaderCode
CustomInclude
CustomSource
CustomLibrary
CustomInitializer
CustomTerminator
IncludeHyperlinkInReport
off
LaunchReport
off
TargetLang
C
IncludeRootSignalInRTWFile
off
IncludeVirtualBlocksInRTWFileBlockHierarchyMap
off
IncludeRegionsInRTWFileBlockHierarchyMap
off
IncludeERTFirstTime
off
GenerateTraceInfo
off
GenerateTraceReport
off
GenerateTraceReportSl
off
GenerateTraceReportSf
off
GenerateTraceReportEml
off
GenerateCodeInfo
off
RTWCompilerOptimization
Off
ObjectivePriorities
RTWCustomCompilerOptimizations
CheckMdlBeforeBuild
Off
CustomRebuildMode
OnUpdate
DataInitializer
Property
Value
Description
HDL Coder custom
configuration component
Components
Name
HDL Coder
Property
Value
Description
Components
Name
SimEvents
SimEventsActiveTab
0
propIdentEvents
0
propIdentEventSeed
123456789
propUnconnectedPorts
0
propMaxDesBlkSimulEvents
1000
propMaxDesMdlSimulEvents
100000
propDiagAttribOutput
0
propDiagFcnCallOutput
1
propDiagStatOutput
0
propDiagChangeAttrib
2
propRNGIdenticalSeeds
1
Property
Value
Name
Code Appearance
Description
Components
Comment
ForceParamTrailComments
off
GenerateComments
on
IgnoreCustomStorageClasses
on
IgnoreTestpoints
off
IncHierarchyInIds
off
MaxIdLength
31
PreserveName
off
PreserveNameWithParent
off
ShowEliminatedStatement
off
IncAutoGenComments
off
SimulinkDataObjDesc
off
SFDataObjDesc
off
MATLABFcnDesc
off
IncDataTypeInIds
off
PrefixModelToSubsysFcnNames
on
MangleLength
1
CustomSymbolStr
$R$N$M
CustomSymbolStrGlobalVar
$R$N$M
CustomSymbolStrType
$N$R$M
CustomSymbolStrField
$N$M
CustomSymbolStrFcn
$R$N$M$F
CustomSymbolStrFcnArg
rt$I$N$M
CustomSymbolStrBlkIO
rtb_$N$M
CustomSymbolStrTmpVar
$N$M
CustomSymbolStrMacro
$R$N$M
CustomCommentsFcn
DefineNamingRule
None
DefineNamingFcn
ParamNamingRule
None
ParamNamingFcn
SignalNamingRule
None
SignalNamingFcn
InsertBlockDesc
off
InsertPolySpaceComments
off
SimulinkBlockComments
on
MATLABSourceComments
off
EnableCustomComments
off
InlinedPrmAccess
Literals
ReqsInCode
off
UseSimReservedNames
off
ReservedNameArray
Property
Value
Name
Target
Description
Components
IsERTTarget
off
TargetFcnLib
ansi_tfl_table_tmw.mat
TargetLibSuffix
TargetPreCompLibLocation
GenFloatMathFcnCalls
ANSI_C
TargetFunctionLibrary
ANSI_C
UtilityFuncGeneration
Auto
ERTMultiwordTypeDef
System defined
ERTCodeCoverageTool
None
ERTMultiwordLength
256
MultiwordLength
2048
GenerateFullHeader
on
GenerateSampleERTMain
off
GenerateTestInterfaces
off
IsPILTarget
off
ModelReferenceCompliant
on
ParMdlRefBuildCompliant
on
CompOptLevelCompliant
on
IncludeMdlTerminateFcn
on
GeneratePreprocessorConditionals
Disable all
CombineOutputUpdateFcns
off
CombineSignalStateStructs
off
SuppressErrorStatus
off
ERTFirstTimeCompliant
off
IncludeFileDelimiter
Auto
ERTCustomFileBanners
off
SupportAbsoluteTime
on
LogVarNameModifier
rt_
MatFileLogging
on
MultiInstanceERTCode
off
SupportNonFinite
on
SupportComplex
on
PurelyIntegerCode
off
SupportContinuousTime
on
SupportNonInlinedSFcns
on
SupportVariableSizeSignals
off
ParenthesesLevel
Nominal
PortableWordSizes
off
GenerateClassInterface
off
ModelStepFunctionPrototypeControlCompliant
off
CPPClassGenCompliant
off
AutosarCompliant
off
ExtMode
off
ExtModeStaticAlloc
off
ExtModeTesting
off
ExtModeStaticAllocSize
1000000
ExtModeTransport
0
ExtModeMexFile
ext_comm
ExtModeMexArgs
ExtModeIntrfLevel
Level1
RTWCAPISignals
off
RTWCAPIParams
off
RTWCAPIStates
off
GenerateASAP2
off
Table 5-14. HDL Coder
Property
Value
HDLSubsystem
sedemo_variable_entity_replication
CoeffPrefix
coeff
InputType
std_logic_vector
OutputType
Same as input type
ScalarizePorts
off
CoeffMultipliers
Multiplier
ResetType
Asynchronous
FIRAdderStyle
linear
MultiplierInputPipeline
0
MultiplierOutputPipeline
0
OptimizeForHDL
off
TimingControllerPostfix
_tc
OptimizeTimingController
on
CastBeforeSum
on
CheckHDL
off
EnablePrefix
enb
ClockEnableInputPort
clk_enable
ClockEnableOutputPort
ce_out
ClockInputPort
clk
ResetInputPort
reset
SimulatorFlags
HDLCompileFilePostfix
_compile.do
HDLCompileInit
vlib %s\n
HDLCompileTerm
HDLCompileVerilogCmd
vlog %s %s\n
HDLCompileVHDLCmd
vcom %s %s\n
HDLMapFilePostfix
_map.txt
HDLMapSeparator
HDLSimCmd
vsim -novopt
work.%s\n
HDLSimFilePostfix
_sim.do
HDLSimProjectFilePostfix
_init.do
HDLSimInit
onbreak resume\nonerror
resume\n
HDLSimProjectCmd
project addfile %s\n
HDLSimProjectTerm
project compileall\n
HDLSimProjectInit
project new . %s
work\n
HDLSimTerm
run -all\n
HDLSimViewWaveCmd
add wave sim:%s\n
HDLSynthCmd
add_file %s\n
HDLSynthFilePostfix
_synplify.tcl
HDLSynthInit
project -new %s.prj\n
HDLSynthTerm
set_option -technology
VIRTEX4\nset_option -part XC4VSX35\nset_option
-synthesis_onoff_pragma 0\nset_option -frequency auto\nproject -run
synthesis\n
ReservedWordPostfix
_rsvd
BlockGenerateLabel
_gen
VHDLLibraryName
work
VHDLArchitectureName
rtl
ClockProcessPostfix
_process
ComplexImagPostfix
_im
ComplexRealPostfix
_re
EntityConflictPostfix
_block
InstancePrefix
u_
InstancePostfix
InstanceGenerateLabel
_gen
OutputGenerateLabel
outputgen
PackagePostfix
_pkg
SplitEntityArch
off
SplitEntityFilePostfix
_entity
SplitArchFilePostfix
_arch
VectorPrefix
vector_of_
ClockInputs
Single
UseRisingEdge
off
TargetDirectory
hdlsrc
EDAScriptGeneration
on
HDLControlFiles
AddInputRegister
on
AddOutputRegister
on
AddPipelineRegisters
off
PipelinePostfix
_pipe
InputPort
filter_in
OutputPort
filter_out
FracDelayPort
filter_fd
Name
filter
RemoveResetFrom
None
ReuseAccum
off
ScaleWarnBits
3
SerialPartition
-1
DALUTPartition
-1
DARadix
2
CoefficientSource
Internal
CoefficientMemory
Registers
InputComplex
off
AddRatePort
off
GenerateCode
on
GenerateModel
on
GenerateTB
off
Traceability
off
ResourceReport
off
OptimizationReport
off
Recommendations
off
RequirementComments
on
Backannotation
off
HandleAtomicSubsystem
on
OptimizeMdlGen
on
MulticyclePathInfo
off
EnableFPGAWorkflow
off
FPGAWorkflowParameters
GainMultipliers
Multiplier
ProductOfElementsStyle
linear
UserComment
ResetAssertedLevel
Active-high
SafeZeroConcat
on
SumOfElementsStyle
linear
TargetLanguage
VHDL
Oversampling
1
Verbosity
1
TestBenchName
filter_tb
MultifileTestBench
off
IgnoreDataChecking
0
TestBenchPostfix
_tb
TestBenchDataPostfix
_data
TestBenchStimulus
TestBenchUserStimulus
TestBenchFracDelayStimulus
TestBenchCoeffStimulus
TestBenchRateStimulus
ForceClockEnable
on
MinimizeClockEnables
off
TestBenchClockEnableDelay
1
ForceClock
on
ClockHighTime
5
ClockLowTime
5
HoldTime
2
ForceReset
on
ErrorMargin
4
HoldInputDataBetweenSamples
on
InitializeTestBenchInputs
off
ResetLength
2
TestBenchReferencePostFix
_ref
GenerateValidationModel
off
BalanceDelays
off
GenerateCoSimBlock
off
GenerateHDLTestBench
on
GenerateCoSimModel
None
CoSimModelSetup
CosimBlockAndDut
SynthesisOnDirective
SynthesisOffDirective
LoopUnrolling
off
InlineConfigurations
on
UseAggregatesForConst
off
UseVerilogTimescale
on
VerilogFileExtension
.v
VHDLFileExtension
.vhd
CodeGenerationOutput
GenerateHDLCode
GeneratedModelName
GeneratedModelNamePrefix
gm_
UseDotLayout
off
ShowCodeGenPIR
off
SerializeModel
0
SerializeIO
0
UseSLAutoRoute
on
HighlightAncestors
on
HighlightColor
cyan
InitializeBlockRAM
on
InitializeRealPort
off
LowerToDirectEmission
off
TurnkeyWorkflow
off
AlteraWorkflow
off
CoSimLibPostfix
_cosim
TestBenchInitializeInputs
off
Chapter 6. Glossary
Atomic Subsystem. A subsystem treated as a unit by an
implementation of the design documented in this report. The
implementation computes the outputs of all the blocks in the atomic
subsystem before computing the next block in the parent system's
block execution order (sorted list).
Block Diagram. A Simulink block diagram represents a set
of simultaneous equations that relate a system or subsystem's
inputs to its outputs as a function of time. Each block in the
diagram represents an equation of the form y = f(t, x, u) where t
is the current time, u is a block input, y is a block output, and x
is a system state (see the Simulink documentation for information
on the functions represented by the various types of blocks that
make up the diagram). Lines connecting the blocks represent
dependencies amonng the blocks, i.e., inputs whose current values
are the outputs of other blocks. An implementation of a design
described in this document computes a root or atomic system's
outputs at each time step by computing the outputs of the blocks in
an order determined by block input/output dependencies.
Block Parameter. A variable that determines the output of
a block along with its inputs, for example, the gain parameter of a
Gain block.
Block Execution Order. The order in which Simulink
evaluates blocks during simulation of a model. The block execution
order determined by Simulink ensures that a block executes only
after all blocks on whose outputs it depends are executed.
Checksum. A number that indicates whether different
versions of a model or atomic subsystem differ functionally or only
cosmetically. Different checksums for different versions of the
same model or subsystem indicate that the versions differ
functionally.
Design Variable. A symbolic (MATLAB) variable or
expression used as the value of a block parameter. Design variables
allow the behavior of the model to be altered by altering the value
of the design variable.
Signal. A block output, so-called because block outputs
typically vary with time.
Virtual Subsystem. A subsystem that is purely graphical,
i.e., is intended to reduce the visual complexity of the block
diagram of which it is a subsystem. An implementation of the design
treats the blocks in the subsystem as part of the first nonvirtual
ancestor of the virtual subsystem (see Atomic Subsystem).
Chapter 7. About this Report
7.1. Report Overview
This report describes the design of the
sedemo_variable_entity_replication system. The report was generated
automatically from a Simulink model used to validate the design. It
contains the following sections:
Model Version. Specifies information about the version of
the model from which this design description was generated.
Includes the model checksum, a number that indicates whether
different versions of the model differ functionally or only
cosmetically. Different checksums for different versions indicate
that the versions differ functionally.
Root System. Describes the design's root system.
Subsystems. Describes each of the design's
subsystems.
Design Variables. Describes system design variables,
i.e., MATLAB variables and expressions used as block parameter
values.
System Model Configuration. Lists the configuration
parameters, e.g., start and stop time, of the model used to
simulate the system described by this report.
Requirements Traceability. Shows design requirements
associated with elements of the design model. This section appears
only if the design model contains requirements links.
Glossary. Defines Simulink terms used in this report.
7.2. Root System Description
This section describes a design's root system. It contains the
following sections:
Diagram. Simulink block diagram that represents the
algorithm used to compute the root system's outputs.
Description. Description of the root system. This section
appears only if the model's root system has a Documentation
property or a Doc block.
Interface. Name, data type, width, and other properties
of the root system's input and output signals. The number of the
block port that outputs the signal appears in angle brackets
appended to the signal name. This section appears only if the root
system has input or output ports.
Blocks. This section has two subsections:
• Parameters. Describes key parameters of blocks in the
root system. This section also includes graphical and/or tabular
representations of lookup table data used by lookup table blocks,
i.e., blocks that use lookup tables to compute their outputs.
• Block Execution Order. Order in which blocks must be
executed at each time step in order to ensure that each block's
inputs are available when it executes.
State Charts. Describes state charts used in the root
system. This section appears only if the root system contains
Stateflow blocks.
7.3. Subsystem Descriptions
This section describes a design's subsystems. Each subsystem
description contains the following sections:
Checksum. This section appears only if the subsystem is
an atomic subsystem. The checksum indicates whether the version of
the model subsystem used to generate this report differs
functionally from other versions of the model subsystem. If two
model checksums differ, the corresponding versions of the model
differ functionally.
Diagram. Simulink block diagram that graphically
represents the algorithm used to compute the subsystem's
outputs.
Description. Description of the subsystem. This section
appears only if the subsystem has a Documentation property or
contains a Doc block.
Interface. Name, data type, width, and other properties
of the subsystem's input and output signals. The number of the
block port that outputs the signal appears in angle brackets
appended to the signal name. This section appears only if the
subsystem is atomic and has input or output ports.
Blocks. Blocks that this subsystem contains. This section
has two subsections:
• Parameters. Key parameters of blocks in the subsystem.
This section also includes graphical and/or tabular representations
of lookup table data used by lookup table blocks, blocks that use
lookup tables to compute their outputs.
• Block Execution Order. Order in which the subsystem's
blocks must be executed at each time step in order to ensure that
each block's inputs are available when the block executes .This
section appears only if the subsystem is atomic.
State Charts. Describes state charts used in the
subsystem. This section appears only if the root system contains
Stateflow blocks.
7.4. State Chart Descriptions
This section describes the state machines used by Stateflow
blocks to compute their outputs, i.e., Stateflow blocks. Each state
machine description contains the following sections:
Chart. Diagram representing the state machine.
States. Describes the state machine's states. Each state
description includes the state's diagram and diagrams and/or
descriptions of graphical functions, Simulink functions, truth
tables, and Embedded MATLAB functions parented by the state.
Transitions. Transitions between the state machine's
states. Each transition description specifies the values of key
transition properties. Appears only if a transition has properties
that do not appear on the chart.
Junctions. Transition junctions. Each junction
description specifies the values of key junction properties.
Appears only if a junction has properties that do not appear on the
chart.
Events. Events that trigger state transitions. Each event
description specifies the values of key event properties.
Data. Data types and other properties of the Stateflow
block's inputs, outputs, and other state machine data.
Targets. Executable implementations of the state machine
used to compute the outputs of the corresponding Stateflow
block.
Embedded MATLAB Supporting Functions. List of functions
invoked by Embedded MATLAB functions defined in the chart.
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