VHDL硬件描述语言实现数字钟

--VHDL上机的一个作业,程序太长实验报告册上写不下了。于是就在博客上留一份吧。
LIBRARY
IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CLOCK IS PORT(CLK1S,SET,SWC,CLK1MS,RST:IN STD_LOGIC; S0,S1,M0,M1,H0,H1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); BEEP:OUT STD_LOGIC; PNS,PSS,PSM,PSH:OUT STD_LOGIC ); END CLOCK; ARCHITECTURE ONE OF CLOCK IS SIGNAL CS,CM:STD_LOGIC;--,CM SIGNAL CLKSI,CLKMI,CLKHI:STD_LOGIC; SIGNAL NS,SS,SM,SH:STD_LOGIC; BEGIN PSS<=SS; PSM<=SM; PSH<=SH; PNS<=NS; PROCESS(SWC,RST) VARIABLE STAT:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN IF(RST='1')THEN STAT:="00"; NS<='1'; SS<='0'; SM<='0'; SH<='0'; ELSIF(RISING_EDGE(SWC))THEN STAT:=STAT+1; CASE STAT IS WHEN"00"=> NS<='1'; SS<='0'; SM<='0'; SH<='0'; WHEN"01"=> NS<='0'; SS<='1'; SM<='0'; SH<='0'; WHEN"10"=> NS<='0'; SS<='0'; SM<='1'; SH<='0'; WHEN"11"=> NS<='0'; SS<='0'; SM<='0'; SH<='1'; WHEN OTHERS=> STAT:="00"; END CASE; END IF; END PROCESS; CLKSI<=(CLK1S AND NS) OR (SS AND SET); CLKMI<=CS OR (SM AND SET); CLKHI<=CM OR (SH AND SET); PROCESS(CLKSI,RST,SET,NS) VARIABLE SS0,SS1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF(RST='1')THEN SS0:="0000"; SS1:="0000"; CS<='0'; --CM<='0'; ELSIF(RISING_EDGE(CLKSI))THEN SS0:=SS0+1; IF(SS0="1010")THEN SS0:="0000"; SS1:=SS1+1; END IF; IF(SS1="0110")THEN SS1:="0000"; --SM0:=SM0+1; CS<='1'; ELSE CS<='0'; END IF; END IF; S0<=SS0; S1<=SS1; END PROCESS; PROCESS(RST,CLKMI,SET) VARIABLE SM0,SM1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF(RST='1')THEN SM0:="0000"; SM1:="0000"; CM<='0'; ELSIF(RISING_EDGE(CLKMI))THEN SM0:=SM0+1; IF(SM0="1010")THEN SM0:="0000"; SM1:=SM1+1; END IF; IF(SM1="0110")THEN SM1:="0000"; CM<='1'; ELSE CM<='0'; END IF; END IF; M0<=SM0; M1<=SM1; END PROCESS; PROCESS(RST,CLKHI,SET) VARIABLE SH0,SH1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF(RST='1')THEN SH0:="0000"; SH1:="0000"; ELSIF(RISING_EDGE(CLKHI))THEN SH0:=SH0+1; IF(SH0="1010")THEN SH0:="0000"; SH1:=SH1+1; END IF; IF(SH1="0010" AND SH0="0100")THEN SH1:="0000"; SH0:="0000"; END IF; END IF; H0<=SH0; H1<=SH1; END PROCESS; PROCESS(CM,CS) BEGIN IF(CM='1' AND CS='1')THEN BEEP<=CLK1MS; ELSE BEEP<='0'; END IF; END PROCESS; END ONE;

 

转载于:https://www.cnblogs.com/cj695/p/3428198.html

第1 章绪 论 ....................................................................................................................1 § 1.1 关于EDA...............................................................................................................1 § 1.2 关于 VHDL............................................................................................................3 § 1.3 关于自顶向下的系统设计方法 ............................................................................5 § 1.4 关于应用 VHDL 的EDA 过程.............................................................................6 § 1.5 关于在系统编程技术 ............................................................................................9 § 1.6 关于 FPGA/CPLD 的优势...................................................................................10 § 1.7 关于 VHDL 的学习.............................................................................................10 第2 章 VHDL 入门..............................................................................................................12 § 2.1 用 VHDL 设计多路选择器和锁存器.................................................................12 § 2.2 用 VHDL 设计全加器.........................................................................................15 第3 章 VHDL 程序结构......................................................................................................19 § 3.1 实 体 ENTITY ..............................................................................................19 § 3.2 结构体 ARCHITECTURE ............................................................................26 § 3.3 块语句结构 BLOCK .....................................................................................29 § 3.4 进程 PROCESS .............................................................................................32 § 3.5 子程序(SUBPROGRAM)....................................................................................35 3.5.1 函数FUNCTION ..................................................................................36 3.5.2
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