HelloWorld 实验
硬件环境：百科融创 嵌入式DSP+ARM实验开发系统(DSP芯片：TMS320C5410A)
软件环境：CCS Studio V3.3
1.打开CCS软件，创建一个工程——HelloWorld
选择Project——New命令，打开工程项目对话框，在Project框中键入要创建的工程项目名HelloWorld。如下图：
2.编写文件
选择File——New——Source File命令，在CCS窗口上分别编辑文件HelloWorld.c 、C54xx.h 、vectors.asm 以及C54xx.cmd，文件建好后分别存放到新建的文件夹
下。
（1）编写C源文件 HelloWorld.c
1 /*********** inluce head files ***************/
2 #include <std.h>
3 #include <stdio.h>
4 #include "c54xx.h"
5
6 /********************************************/
7 void main()
8 {
9 unsigned int i,j;
10 unsigned int Print_Num = 0;
11 while(1)
12 {
13 printf("%d\t--Hello World!\n", Print_Num++);
14 for(i=0; i<50; i++)
15 for(j=0; j<10000; j++);
16
17 }
18 }
(2)编写复位向量文件 vectors.asm
vectors.asm
1 .sect ".vectors"
2
3 .ref _c_int00 ; C entry point
4
5 .align 0x80 ; must be aligned on page boundary
6
7 RESET: ; reset vector
8 BD _c_int00 ; branch to C entry point
9 STM #200,SP ; stack size of 200
10 nmi: RETE ; enable interrupts and return from one
11 NOP
12 NOP
13 NOP ;NMI~
14
15 ; software interrupts
16 sint17 .space 4*16
17 sint18 .space 4*16
18 sint19 .space 4*16
19 sint20 .space 4*16
20 sint21 .space 4*16
21 sint22 .space 4*16
22 sint23 .space 4*16
23 sint24 .space 4*16
24 sint25 .space 4*16
25 sint26 .space 4*16
26 sint27 .space 4*16
27 sint28 .space 4*16
28 sint29 .space 4*16
29 sint30 .space 4*16
30
31 int0: RETE ;External user interrupt #0
32 NOP
33 NOP
34 NOP
35 int1: RETE ;External user interrupt #1
36 NOP
37 NOP
38 NOP
39 int2: RETE ;External user interrupt #2
40 NOP
41 NOP
42 NOP
43 tint: RETE ;Timer interrupt
44 NOP
45 NOP
46 NOP
47 rint0: RETE ;McBSP #0 receive interrupt (default)
48 NOP
49 NOP
50 NOP
51 xint0: RETE ;McBSP #0 transmit interrupt (default)
52 NOP
53 NOP
54 NOP
55 rint2: RETE ;McBSP #2 receive interrupt (default)
56 NOP
57 NOP
58 NOP
59 xint2: RETE ;McBSP #2 transmit interrupt (default)
60 NOP
61 NOP
62 NOP
63 int3: RETE ;External user interrupt #3
64 NOP
65 NOP
66 NOP
67 hint: RETE ;HPI interrupt
68 NOP
69 NOP
70 NOP
71 rint1: RETE ;McBSP #1 receive interrupt (default)
72 NOP
73 NOP
74 NOP
75 xint1: RETE ;McBSP #1 transmit interrupt (default)
76 NOP
77 NOP
78 NOP
79 .space 16*16
80 .end
(3)编写链接文件 C54xx.cmd
C54xx.cmd
1 MEMORY
2 {
3 PAGE 0: EPROG: origin = 0x4000, len = 0x3f80
4 VECT: origin = 0x7f80, len = 0x80
5
6 PAGE 1: SYSREGS: origin = 0x00, len = 0x60
7 BIOSREGS: origin = 0x60, len = 0x20
8 IDATA: origin = 0x80, len = 0x3f00
9 EDATA: origin = 0x8000, len = 0x8000
10 }
11
12 SECTIONS
13 {
14 .vectors: {} > VECT PAGE 0
15 .sysregs: {} > BIOSREGS PAGE 1
16 .text: {} > EPROG PAGE 0
17 .cinit: {} > EPROG PAGE 0
18 .bss: {} > IDATA PAGE 1
19 .const: {} > IDATA PAGE 1
20 .switch: {} > IDATA PAGE 1
21 .sysmem: {} > IDATA PAGE 1
22 .stack: {} > IDATA PAGE 1
23 }
（4）编写头文件 C54xx.h
C54xx.h
1 #ifndef __C54XX_H__
2 #define __C54XX_H__
3
4 #include <std.h>
5
6 #define uint unsigned int
7 #define uchar unsigned char
8 #define ulong unsigned long
9 #define ushort unsigned short
10 #define vuint volatile unsigned int
11 #ifndef NULL
12 #define NULL 0
13 #define FALSE (Bool)0
14 #define TRUE (Bool)1
15 #endif
16
17 /***********************************/
18 /* CPU Memory-Mapped Registers */
19 /***********************************/
20
21 /* Interrupt Flag and Interrupt Mask Registers */
22 #define IMR *(vuint *)0x00
23 #define IMR_ADDR 0x00
24 #define IFR *(vuint *)0x01
25 #define IFR_ADDR 0x01
26
27 /* Status Registers */
28 #define ST0 *(vuint *)0x06
29 #define ST0_ADDR 0x06
30 #define ST1 *(vuint *)0x07
31 #define ST1_ADDR 0x07
32
33 /* Accumulator Registers */
34 #define AL *(vuint *)0x08
35 #define AL_ADDR 0x08
36 #define AH *(vuint *)0x09
37 #define AH_ADDR 0x09
38 #define AG *(vuint *)0x0a
39 #define AG_ADDR 0x0a
40 #define BL *(vuint *)0x0b
41 #define BL_ADDR 0a0b
42 #define BH *(vuint *)0x0c
43 #define BH_ADDR 0x0c
44 #define BG *(vuint *)0x0d
45 #define BG_ADDR 0x0d
46
47 /* Temporary Register */
48 #define T *(vuint *)0x0e
49 #define T_ADDR 0x0e
50
51 /* Transition Register */
52 #define TRN *(vuint *)0x0f
53 #define TRN_ADDR 0x0f
54
55 /* Auxiliary Registers */
56 #define AR0 *(vuint *)0x10
57 #define AR0_ADDR 0x10
58 #define AR1 *(vuint *)0x11
59 #define AR1_ADDR 0x11
60 #define AR2 *(vuint *)0x12
61 #define AR2_ADDR 0x12
62 #define AR3 *(vuint *)0x13
63 #define AR3_ADDR 0x13
64 #define AR4 *(vuint *)0x14
65 #define AR4_ADDR 0x14
66 #define AR5 *(vuint *)0x15
67 #define AR5_ADDR 0x15
68 #define AR6 *(vuint *)0x16
69 #define AR6_ADDR 0x16
70 #define AR7 *(vuint *)0x17
71 #define AR7_ADDR 0x17
72
73 /* Stack Pointer Register */
74 #define SP *(vuint *)0x18
75 #define SP_ADDR 0x18
76
77 /* Circular Buffer Size Register */
78 #define BK *(vuint *)0x19
79 #define BK_ADDR 0x19
80
81 /* Block Repeat Counter */
82 #define BRC *(vuint *)0x1a
83 #define BRC_ADDR 0x1a
84
85 /* Block Repeat Start & End Address */
86 #define RSA *(vuint *)0x1b
87 #define RSA_ADDR 0x1b
88 #define REA *(vuint *)0x1c
89 #define REA_ADDR 0x1c
90
91 /* Processor Mode Status Register */
92 #define PMST *(vuint *)0x1d
93 #define PMST_ADDR 0x1d
94
95 /* Extended Program Page Register */
96 #define XPC *(vuint *)0x1e
97 #define XPC_ADDR 0x1e
98
99 /*****************************************/
100 /* Peripheral Memory-Mapped Registers */
101 /*****************************************/
102
103 /* Timer Registers */
104 #define TIM *(vuint *)0x24
105 #define TIM_ADDR 0x24
106 #define PRD *(vuint *)0x25
107 #define PRD_ADDR 0x25
108 #define TCR *(vuint *)0x26
109 #define TCR_ADDR 0x26
110
111 /* Software Wait-state & Control Registers */
112 #define SWWSR *(vuint *)0x28
113 #define SWWSR_ADDR 0x28
114 #define SWCR *(vuint *)0x2b
115 #define SWCR_ADDR 0x2b
116
117 /* Bank-switching Control Register */
118 #define BSCR *(vuint *)0x29
119 #define BSCR_ADDR 0x29
120
121 /* HPI Control Register */
122 #define HPIC *(vuint *)0x2c
123 #define HPIC_ADDR 0x2c
124
125 /* Registers of McBSP Receive and Transmit*/
126 typedef volatile struct
127 {
128 uint DRR2; /* data receive register */
129 uint DRR1;
130 uint DXR2; /* data transmit register */
131 uint DXR1;
132 } McBSP; /* McBSPB means McBSP Buffer which receive and transmit data */
133
134 #define McBSP0 (*(McBSP *)0x20)
135 #define McBSP1 (*(McBSP *)0x40)
136 #define McBSP2 (*(McBSP *)0x30)
137
138 /* Serial Port Sub-address and Sub-data Registers */
139 #define SPSA0 *(vuint *)0x38
140 #define SPSA0_ADDR 0x38
141 #define SPSD0 *(vuint *)0x39
142 #define SPSD0_ADDR 0x39
143 #define SPSA1 *(vuint *)0x48
144 #define SPSA1_ADDR 0x48
145 #define SPSD1 *(vuint *)0x49
146 #define SPSD1_ADDR 0x49
147 #define SPSA2 *(vuint *)0x34
148 #define SPSA2_ADDR 0x34
149 #define SPSD2 *(vuint *)0x35
150 #define SPSD2_ADDR 0x35
151
152 /* Define Sub-address Name of Serial Port */
153 #define SPCR1 0x00 /* serial port control register */
154 #define SPCR2 0x01
155 #define RCR1 0x02 /* receive control register */
156 #define RCR2 0x03
157 #define XCR1 0x04 /* transmit control register */
158 #define XCR2 0x05
159 #define SRGR1 0x06 /* sample rate generator register */
160 #define SRGR2 0x07
161 #define MCR1 0x08 /* multichannel register */
162 #define MCR2 0x09
163 #define RCERA 0x0a /* receive channel enable register partition A */
164 #define RCERB 0x0b /* receive channel enable register partition B */
165 #define XCERA 0x0c /* transmit channel enable register partition A */
166 #define XCERB 0x0d /* transmit channel enable register partition B */
167 #define PCR 0x0e /* pin control register */
168
169 /* Clock Mode Register */
170 #define CLKMD *(vuint *)0x58
171
172 /* DMA Channel Priority and Enable Control Register */
173 #define DMPREC *(vuint *)0x54
174
175 /* DMA Channel Sub-address Register */
176 #define DMSA *(vuint *)0x55
177
178 /* DMA Data_initiate Registers */
179 #define DMSD1 *(vuint *)0x56
180 #define DMSD2 *(vuint *)0x57
181
182 /* Define Sub-address Name of DMA */
183 #define DMSRC0 0x00 /* DMA channel 0 source address register */
184 #define DMDST0 0x01 /* DMA channel 0 destination address register */
185 #define DMCTR0 0x02 /* DMA channel 0 element count register */
186 #define DMSFC0 0x03 /* DMA channel 0 sync select and frame count register */
187 #define DMMCR0 0x04 /* DMA channel 0 transfer mode control register */
188 #define DMSRC1 0x05 /* DMA channel 1 source address register */
189 #define DMDST1 0x06 /* DMA channel 1 destination address register */
190 #define DMCTR1 0x07 /* DMA channel 1 element count register */
191 #define DMSFC1 0x08 /* DMA channel 1 sync select and frame count register */
192 #define DMMCR1 0x09 /* DMA channel 1 transfer mode control register */
193 #define DMSRC2 0x0a /* DMA channel 2 source address register */
194 #define DMDST2 0x0b /* DMA channel 2 destination address register */
195 #define DMCTR2 0x0c /* DMA channel 2 element count register */
196 #define DMSFC2 0x0d /* DMA channel 2 sync select and frame count register */
197 #define DMMCR2 0x0e /* DMA channel 2 transfer mode control register */
198 #define DMSRC3 0x0f /* DMA channel 3 source address register */
199 #define DMDST3 0x10 /* DMA channel 3 destination address register */
200 #define DMCTR3 0x11 /* DMA channel 3 element count register */
201 #define DMSFC3 0x12 /* DMA channel 3 sync select and frame count register */
202 #define DMMCR3 0x13 /* DMA channel 3 transfer mode control register */
203 #define DMSRC4 0x14 /* DMA channel 4 source address register */
204 #define DMDST4 0x15 /* DMA channel 4 destination address register */
205 #define DMCTR4 0x16 /* DMA channel 4 element count register */
206 #define DMSFC4 0x17 /* DMA channel 4 sync select and frame count register */
207 #define DMMCR4 0x18 /* DMA channel 4 transfer mode control register */
208 #define DMSRC5 0x19 /* DMA channel 5 source address register */
209 #define DMDST5 0x1a /* DMA channel 5 destination address register */
210 #define DMCTR5 0x1b /* DMA channel 5 element count register */
211 #define DMSFC5 0x1c /* DMA channel 5 sync select and frame count register */
212 #define DMMCR5 0x1d /* DMA channel 5 transfer mode control register */
213 #define DMSRCP 0x1e /* DMA source program page address (common channel) */
214 #define DMDSTP 0x1f /* DMA destination program page address (common channel) */
215 #define DMIDX0 0x20 /* DMA element index address register 0 */
216 #define DMIDX1 0x21 /* DMA element index address register 1 */
217 #define DMFRI0 0x22 /* DMA frame index register 0 */
218 #define DMFRI1 0x23 /* DMA frame index register 1 */
219 #define DMGSA 0x24 /* DMA global source address reload register */
220 #define DMGDA 0x25 /* DMA global destination address reload register */
221 #define DMGCR 0x26 /* DMA global count reload register */
222 #define DMGFR 0x27 /* DMA global frame count reload register */
223
224 /* Disable and Enable Interrupt */
225 #define INT_Disable asm(" ssbx intm ")
226 #define INT_Enable asm(" rsbx intm ")
227
228 /* Set and Clear INTM flag */
229 #define SET_INTM asm(" ssbx intm ")
230 #define CLEAR_INTM asm(" rsbx intm ")
231
232 /* Clear OVA & OVB flag */
233 #define CLEAR_OVA asm(" rsbx ova ")
234 #define CLEAR_OVB asm(" rsbx ovb ")
235
236 /* Set and Clear XF flag */
237 #define SET_XF asm(" ssbx xf ")
238 #define CLEAR_XF asm(" rsbx xf ")
239
240 /* Set and Clear OVM flag */
241 #define SET_OVM asm(" ssbx ovm ")
242 #define CLEAR_OVM asm(" rsbx ovm ")
243
244 /* Set and Clear SXM flag */
245 #define SET_SXM asm(" ssbx sxm ")
246 #define CLEAR_SXM asm(" rsbx sxm ")
247
248 /* Set and Clear C16 flag */
249 #define SET_C16 asm(" ssbx c16 ")
250 #define CLEAR_C16 asm(" rsbx c16 ")
251
252 /* Set and Clear OVM flag */
253 #define SET_OVM asm(" ssbx ovm ")
254 #define CLEAR_OVM asm(" rsbx ovm ")
255
256 /* Set and Clear FRCT flag */
257 #define SET_FRCT asm(" ssbx frct ")
258 #define CLEAR_FRCT asm(" rsbx frct ")
259
260 /* Set and Clear CMPT flag */
261 #define SET_CMPT asm(" ssbx cmpt ")
262 #define CLEAR_CMPT asm(" rsbx cmpt ")
263
264 /* Set and Clear CPL flag */
265 #define SET_CPL asm(" ssbx cpl ")
266 #define CLEAR_CPL asm(" rsbx cpl ")
267
268 /* Set and Clear HM flag */
269 #define SET_HM asm(" ssbx hm ")
270 #define CLEAR_HM asm(" rsbx hm ")
271
272 /* Set and Clear OVLY flag */
273 #define SET_BRAF asm(" ssbx braf ")
274 #define CLEAR_BRAF asm(" rsbx braf ")
275
276 /* IDLE Mode */
277 #define IDLE1 asm(" idle 1 ")
278 #define IDLE2 asm(" idle 2 ")
279 #define IDLE3 asm(" idle 3 ")
280
281 /* End of c54_zzh.h */
282
283 #endif
3.向工程项目添加文件
选择Project——Add File to Project命令，将以下4个文件添加到当前工程项目中
C语言源文件：HelloWorld.c
复位向量文件：vectors.asm
链接命令文件：c54xx.cmd
头文件：c54xx.h
如下图所示：
再将D:\CCStudio_v3.3\C5400\cgtools\lib 下1个C语言的标准支持库文件rts.lib添加到工程项目中。如下图：
向工程项目添加文件之后，工程窗口中的文件列表如下图所示：
4.构建工程和加载可执行文件
对工程项目中的文件进行编译、汇编、链接，生成可以在目标系统中运行的、可执行的输出文件(HelloWorld.out)。
点击File下的Load Program命令，选择本工程目录下的Debug文件夹下面的HelloWorld.out文件，点击【打开】，即可将该工程编译后的可执行文件加载到DSP内部的SRAM中。如下图：
5.运行应用程序
单击调试工具栏按钮“Run”，便可启动DSP执行本工程编译的代码，执行结果如下图所示：
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