BCM5396的SPI理解

 

参考文档链接:https://pan.baidu.com/s/1kuXJmULwtjOW1TeOuTRPQQ

*时钟极性和相位

BCM538X / BCM5396用于根据以下标准发送/接收SPI数据:
•时钟极性(CPOL)= 0或1 ;
•时钟相位(CPHA)= 1 ;
CPOL由SS在空闲状态下从高电平变为低电平时SCK的值确定。

这些参数在BCM538X / BCM5396上不可编程。 外部SPI器件需要与BCM538X / BCM5396的参数保持一致才能正常通信。
时钟极性 (CPOL)- 如果此参数为1,则SCK相对于主设备的内部移位时钟反转。 如果此参数为0,则SCK空闲状态为低。 如果CPOL = 1,则SCK空闲状态为高。
时钟相位 (CPHA)- 如果此参数为1,则SCK相对于主机的内部移位时钟相移180°。 假设CPOL = 0,则如果此参数为0,则数据在SCK上升沿锁定。 如果此参数为1,则数据在SCK下降沿锁定。 如果CPOL = 1,则与CPOL=0相反。
有关CPOL和CPHA的信息,请参阅Motorola™SPI接口规范。

 

 

 

       

 

    

 

 *BCM5396采样边沿

    SS由0到1时,SCLK=1,故CPOL=1;同时BCM的CPHA固定为1;因而,是SCLK的上升沿进行采样;

 

 

*BCM5396操作时序:

 

 

 

 

转载于:https://www.cnblogs.com/limanjihe/p/9893220.html

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Single-Chip 16-Port SerDes Gigabit Switch.The BCM5396 is a 16-port Gigabit Ethernet (GbE) switch integrated with 16 1.25G SerDes/SGMII port interfaces for connecting to external Gigabit PHYs or fiber modules. The BCM5396 provides the lowestcost GbE functionality to the desktop switching solution or WebSmart™ application. The BCM5396 is a highly integrated solution, combining all of the functions of a high-speed switch system, including packet buffer, Media Access Controllers (MACs), address management, and a nonblocking switch controller into a single monolithic 0.13 µm CMOS device. The BCM5396 complies with the IEEE 802.3™, 802.3u, 802.3ab, and 802.3x specifications, including the MAC control PAUSE frame and auto-negotiation subsections, providing compatibility with all industry-standard Ethernet, Fast Ethernet, and GbE devices. The BCM5396 device provides integrated 1.25G SerDes, reducing board footprint requirements. The 16 ports have SGMII interfaces for connecting with external GbE transceivers. 16-port 10/100/1000 Mbps integrated switch controller via 1.25G SerDes/SGMII/fiber • Embedded 256 KB on-chip packet buffer • One 10/100/1000 Mbps In-band Management Port (IMP) with GMII/RGMII/RvMII/MII interface for PHY-less connection to a CPU/management entity (for management purposes only) • Integrated address management • Supports up to 4K MAC addresses • Supports jumbo frames up to 9728 bytes. • Supports EEPROM for low-cost chip configuration • Integrated Motorola® SPI-compatible interface • Supports port mirroring • Port-based VLAN and 4K IEEE 802.1Q tag VLAN • Port-, DiffServ-, MAC-, and IEEE 802.1p-based QoS for four queues • Supports Spanning Tree, Rapid Spanning Tree, and Multiple Spanning Tree protocols (802.1D/1s/1w) • Supports IEEE Standard 802.1X port security • Supports pseudo-PHY MDIO access • MAC-based trunking with link fail-over • Ethernet-in-the-last-mile (EFM) support: OAM and P • Low-power (2.2W total) 1.2V core/2.5V (SGMII I/ O)/3.3V (GMII/MII/RvMII) and 2.5V RGMII operation with 3.3V I/O tolerance • 256-pin FBGA package
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