Linux Makefile Howto

<?xml version="1.0" encoding="utf-8"?> Linux Makefile Howto

Linux Makefile Howto

As far as I can remember, I have worked with makefile for quite a while, and I will look up for the meaning of all kinds of symbols in it, and after a thorough understanding of one makefile and the combination of a makefile I used most, I will post my own version of the makefile.

I will borrow the example I found on the Internet.(A Simple Makefile Tutorial) and (makefile by examples)

The following files are needed to make the compilation correct:

hellomake.h

extern void print_hello(void);

print_fun.c

#include <stdio.h>
#include <stdlib.h>

void print_hello(void)
{
    printf("Hello make world!\n");
}

main.c

#include "hellomake.h"

int main(void)
{
    print_hello();
}

In a typical small or medium sized project, these directories are needed:

name	function
src	all the c or cpp files
src/obj	the compiler generated object files, which are normally correspondents with src files
exe	the final output of the project
libs	the external libs the project needs
include	all the .h files needed by other .c files

The src/Makefile has the following contents:

CC=gcc
IDIR = ../include
CFLAGS=-I$(IDIR)

ODIR = obj
LDIR = ../libs

LIBS = -lm

_DEPS = hellomake.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

SOURCES = $(wildcard *.c)
_OBJ = $(SOURCES:.c=.o)
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

EXE = hellomake
EXEDIR = ../exe

$(ODIR)/%.o: %.c $(DEPS)
    $(CC) -c -o $@ $< $(CFLAGS)

$(EXEDIR)/$(EXE): $(OBJ)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY:clean

clean:
    rm -f $(ODIR)/*.o $(EXEDIR)/$(EXE)

A fe-fined version of the makefile looks like:

CC=gcc
IDIR = ../include
CFLAGS=-I$(IDIR)
ODIR = obj
LDIR = ../libs
EXEDIR = ../exe
LIBS = -lm
DEPS = $(IDIR)/$(wildcard *.h)          
SOURCES = $(wildcard *.c)
_OBJ = $(SOURCES:.c=.o)
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

#the name of the executable file should be changed when used in a specific project
EXE = hellomake

$(ODIR)/%.o: %.c $(DEPS)
    $(CC) -c -o $@ $< $(CFLAGS)

$(EXEDIR)/$(EXE): $(OBJ)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY:clean

clean:
    rm -f $(ODIR)/*.o $(EXEDIR)/$(EXE)

#make project-dir-tree is used to create the necessary directory structure used in this makefile
project-dir-tree:
    mkdir include libs src src/obj exe
    cp Makefile ./src

In order to use this makefile, you should first create a project directory say, test_project, and you copy the makefile to the newly created directory, then invoke make project-dir-tree the following directories will appear, and you can organize your project clearly.

exe include libs src

But if you are working on a relatively small project which involves only a couple of source files, you can use this simplified version of makefile:

CC=gcc
CFLAGS = -I.
DEFPS = $(wildcard *.h)
SOURCES = $(wildcard *.c)
OBJ = $(SOURCES:.o=.c)
LIBS = -lm

EXE = test

%.o:%.c $(DEPS)
    gcc -c -o $@ $< $(CFLAGS)

$(EXE):$(OBJ)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY:clean

clean:
    rm -rf *.o $(EXE)

With this file in hand, you can modify the desired output of the EXE to get the desired exe-file, and that is all you need do, enjoy it!

By the way, if you don't want to compile all the source files in a directory, you can specify the sources files you want to compile by changing the SOURCES variable, like

SOURCES = a.c b.c

Author: wujing

Created: 2014-08-26 二 10:08

Emacs 24.3.1 (Org mode 8.2.6)

Validate

转载于:https://www.cnblogs.com/wujingcqu/p/3936598.html