Clk=1ns,A=0.3ns,B=0.6ns,C=0.3ns,D=0.2ns,MUX=0.2ns,忽略F的clk-q延时, A->B->MUX是关键路径,0.3+0.6+0.2>1,请修正violation,可复制logic,面积不考虑。 答案: 转载于:https://www.cnblogs.com/zhangzhi/archive/2009/10/24/1589341.html