altera_reserved_tck的问题

今天编译完成后在critical warning出现的关于altera_reserved_tck时序有问题的提示。

配置完FPGA后，然后出现的问题是我在NIOSII IDE SP2的环境下，下载不了elf文件，出现“downloading elf failed”。

怀疑是不是由于tck的问题，导致jtag工作不正常。

下面是摘自altera support solution:

Problem

What timing constraint do I apply to the automatically-generated altera_reserved_tck clock pin in my design?

Solution

The altera_reserved_tck pin is automatically generated for a design that uses a JTAG accessible module such as the SignalTap® II logic analyzer, the In-System Memory Content Editor or the Nios® II debugger.

To constrain this JTAG clock, apply a 10-MHz clock constraint to this pin.

For the TimeQuest Timing Analyzer, use the following command:

create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}

For the Quartus® II Classic Timing Analyzer, use the following command:

set_global_assignment -name FMAX_REQUIREMENT "10 MHz" -section_id altera_reserved_tck
set_instance_assignment -name CLOCK_SETTINGS altera_reserved_tck -to altera_reserved_tck

Any datapaths crossing into the altera_reserved_tck clock domain from another domain can be set as false paths. Similarly any datapaths crossing from the altera_reserved_tck domain to another domain can also be set as false paths.

转载于:https://www.cnblogs.com/lsilkworm/archive/2010/04/02/1703060.html