# fir fpga 不同截止频率_FPGA实现FIR滤波器

1、FIR滤波器总体设计

2、FIR滤波器原理

>> Num

Num =

-0.0325 -0.0384 0.0784 0.2874 0.3984 0.2874 0.0784 -0.0384 -0.0325

>> Num=round(Num*400)//将系数放大并取整

Num =

-13 -15 31 115 159 115 31 -15 -13

>> Num=Num+20//将系数符号变成正的，便于FPGA使用

Num =

7 5 51 135 179 135 51 5 7

3.2 待滤波信号的设计

%*********产生.data文件 用于FPGA仿真************%

Fs = 10000; %采样频率决定了两个正弦波点之间的间隔

N = 4096; %采样点数

N1 = 0 : 1/Fs : N/Fs-1/Fs;

s = sin(1000*2*pi*N1) + sin(3000*2*pi*N1) +sin(4000*2*pi*N1);//三种正弦波

fidc = fopen('D:FPGAFIRmem.txt','wt'); //将结果写入mem.txt文件，便于modesim使用

for x = 1 : N

fprintf(fidc,'%x',round((s(x)+2.12)*58));

end

fclose(fidc);

4、FPGA实现FIR算法

reg[7:0] delay_pipeline1 ;

reg[7:0] delay_pipeline2 ;

reg[7:0] delay_pipeline3 ;

reg[7:0] delay_pipeline4 ;

reg[7:0] delay_pipeline5 ;

reg[7:0] delay_pipeline6 ;

reg[7:0] delay_pipeline7 ;

reg[7:0] delay_pipeline8 ;

reg[7:0] delay_pipeline9 ;

always@(posedge CLK or negedge RSTn)

if(!RSTn)

begin

delay_pipeline1 <= 8'b0 ;

delay_pipeline2 <= 8'b0 ;

delay_pipeline3 <= 8'b0 ;

delay_pipeline4 <= 8'b0 ;

delay_pipeline5 <= 8'b0 ;

delay_pipeline6 <= 8'b0 ;

delay_pipeline7 <= 8'b0 ;

delay_pipeline8<= 8'b0 ;

delay_pipeline9<= 8'b0 ;

end

else

begin

delay_pipeline1 <= FIR_IN ;

delay_pipeline2 <= delay_pipeline1 ;

delay_pipeline3 <= delay_pipeline2 ;

delay_pipeline4 <= delay_pipeline3 ;

delay_pipeline5 <= delay_pipeline4 ;

delay_pipeline6 <= delay_pipeline5 ;

delay_pipeline7 <= delay_pipeline6 ;

delay_pipeline8 <=delay_pipeline7 ;

delay_pipeline9<= delay_pipeline8 ;

end

wire[7:0] coeff1 = 8'd7; //滤波器系数

wire[7:0] coeff2 = 8'd5;

wire[7:0] coeff3 = 8'd51;

wire[7:0] coeff4 = 8'd135;

wire[7:0] coeff5 = 8'd179;

wire[7:0] coeff6 = 8'd135;

wire[7:0] coeff7 = 8'd51;

wire[7:0] coeff8 = 8'd5;

wire[7:0] coeff9 = 8'd7;

reg signed [16:0] multi_data1 ;//乘积结果

reg signed [16:0] multi_data2 ;

reg signed [16:0] multi_data3 ;

reg signed [16:0] multi_data4 ;

reg signed [16:0] multi_data5 ;

reg signed [16:0] multi_data6 ;

reg signed [16:0] multi_data7 ;

reg signed [16:0] multi_data8 ;

reg signed [16:0] multi_data9 ;

always@(posedge CLK or negedge RSTn) //x(0) * h(0)

if(!RSTn)

multi_data1 <= 17'b0 ;

else

multi_data1 <= delay_pipeline1*coeff1 ;

always@(posedge CLK or negedge RSTn) //x(1) * h(1)

if(!RSTn)

multi_data2 <= 17'b0 ;

else

multi_data2 <= delay_pipeline2*coeff2 ;

//===================================================================

//加法器

//===================================================================

always@(posedge CLK or negedge RSTn)

if(!RSTn)

FIR_OUT <= 16'b0 ;

else

FIR_OUT <= multi_data1 + multi_data2 + multi_data3 + multi_data4 +multi_data5 + multi_data6 + multi_data7 + multi_data8 + multi_data9 ;

4、仿真结果

4.1 MATLAB仿真结果

Fs = 10000; %采样频率决定了两个正弦波点之间的间隔

N = 4096; %采样点数

N1 = 0 : 1/Fs :N/Fs-1/Fs;

in =sin(1000*2*pi*N1) + sin(3000*2*pi*N1) + sin(4000*2*pi*N1);

coeff =[-0.0325,-0.0384,0.0784,0.2874,0.3984,0.2874,0.0784,-0.0384,-0.0325];

out =conv(in,coeff);%卷积滤波

subplot(2,1,1);

plot(in);

xlabel('滤波前');

axis([0 200 -33]);

subplot(2,1,2);

plot(out);

xlabel('滤波后');

axis([100 200 -22]);

Modesim仿真结果

module FIR_vlg_tst();

reg CLK;

reg [7:0] FIR_IN;

reg RSTn;

reg [7:0] mem[1:4096];

wire [15:0] FIR_OUT;

reg [12:0] i;

FIR i1 (

.CLK(CLK),

.FIR_IN(FIR_IN),

.FIR_OUT(FIR_OUT),

.RSTn(RSTn)

);

initial

begin