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project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qpg
25.63 MB
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project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qpg
25.52 MB
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3
project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qpg
23.8 MB
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.sdf
18.17 MB
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project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qtl
13.17 MB
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qtl
5.19 MB
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project_cpu54\project_cpu54.sim\sim_1\impl\func\tb_func_impl.v
4.54 MB
2018/6/14 0:35:13
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.v
3.72 MB
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project_cpu54\project_cpu54.sim\sim_1\behav\result.txt
3.47 MB
2018/7/17 23:55:28
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project_cpu54\project_cpu54.sim\sim_1\synth\func\tb_func_synth.v
3.19 MB
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project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_placed.dcp
3.1 MB
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project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow.dcp
2.25 MB
2018/6/14 16:56:27
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project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_opt.dcp
2.2 MB
2018/6/14 16:57:41
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\simulate.log
1.81 MB
2018/7/18 22:31:02
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.sdf_typ.csd
1.66 MB
2018/7/18 22:26:01
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project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qtl
1.66 MB
2018/6/19 23:51:45
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project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow.dcp
1.53 MB
2018/6/21 0:03:43
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qpg
1.19 MB
2018/7/17 23:54:56
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project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib.qdb
1.05 MB
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project_cpu54\timing_report.txt
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project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qdb
472 KB
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project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_info
360.66 KB
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qtl
324.66 KB
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib.qdb
288 KB
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project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider.xml
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qdb
224 KB
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project_cpu54\project_cpu54.runs\synth_1\vivado.pb
213.29 KB
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project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem_sim_netlist.vhdl
177.87 KB
2018/6/3 16:26:29
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project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dist_mem_gen_v8_0_10\hdl\dist_mem_gen_v8_0_vhsyn_rfs.vhd
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project_cpu54\project_cpu54.srcs\sources_1\ip\imem\dist_mem_gen_v8_0_10\hdl\dist_mem_gen_v8_0_vhsyn_rfs.vhd
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project_cpu54\vivado_pid1524.str
168.65 KB
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project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib.qdb
160 KB
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project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qdb
160 KB
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib1_0.qpg
152 KB
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project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem_sim_netlist.v
133.14 KB
2018/6/3 16:26:29
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project_cpu54\project_cpu54.runs\dmem_synth_1\dmem.dcp
129.68 KB
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project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem.dcp
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project_cpu54\project_cpu54.runs\synth_1\runme.log
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project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow.vds
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\vsim.wlf
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project_cpu54\project_cpu54.sim\sim_1\behav\modelsim.ini
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project_cpu54\project_cpu54.sim\sim_1\impl\func\modelsim.ini
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project_cpu54\project_cpu54.sim\sim_1\synth\func\modelsim.ini
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\modelsim.ini
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project_cpu54\project_cpu54.sim\sim_1\impl\func\simulate.log
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project_cpu54\project_cpu54.sim\sim_1\impl\func\compile.log
92.95 KB
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_info
81.09 KB
2018/7/18 22:25:40
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project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_io_placed.rpt
80.43 KB
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project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider.xci
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project_cpu54\project_cpu54.runs\dmem_synth_1\vivado.pb
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project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem.xml
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project_cpu54\vivado.log
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project_cpu54\vivado_7828.backup.log
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project_cpu54\project_cpu54.srcs\sources_1\ip\imem\imem.xml
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\vsim.wlf
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project_cpu54\project_cpu54.sim\sim_1\impl\func\vsim.wlf
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project_cpu54\project_cpu54.sim\sim_1\synth\func\vsim.wlf
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project_cpu54\project_cpu54.ip_user_files\mem_init_files\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\activehdl\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\ies\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\modelsim\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\questa\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\riviera\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\vcs\imem.mif
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project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\xsim\imem.mif
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project_cpu54\project_cpu54.sim\sim_1\behav\imem.mif
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project_cpu54\project_cpu54.sim\sim_1\synth\func\imem.mif
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\imem.mif
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project_cpu54\project_cpu54.srcs\sources_1\ip\imem\imem.mif
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project_cpu54\project_cpu54.sim\sim_1\impl\func\imem.mif
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project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_info
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project_cpu54\project_cpu54.runs\Divider_synth_1\vivado.pb
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project_cpu54\vivado_12788.backup.log
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project_cpu54\project_cpu54.runs\dmem_synth_1\runme.log
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project_cpu54\project_cpu54.runs\dmem_synth_1\dmem.vds
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib1_0.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib1_0.qdb
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project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib1_0.qpg
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project_cpu54\project_cpu54.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh
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project_cpu54\project_cpu54.runs\Divider_synth_1\runme.log
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project_cpu54\project_cpu54.sim\sim_1\synth\timing\compile.log
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project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_control_sets_placed.rpt
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