Abstract
DE2預設為50MHz,在寫Testbench時,該如何產生50MHz的時脈(clock)呢?
Verilog
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/*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
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4 Filename : Clk_50M.v
5 Compiler : ModelSim SE 6.1f
6 Description : Demo how to generate 50MHz clock
7 Release : 02/10/2008 1.0
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2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : Clk_50M.v
5 Compiler : ModelSim SE 6.1f
6 Description : Demo how to generate 50MHz clock
7 Release : 02/10/2008 1.0
8