verilong 代码中寄存器字长勿省略！

 

例子1：

module exe4(out,E1,addr,d1,d2,d3,d4);
input [1:0] addr;
input d1,d2,d3,d4;
input E1;

output out;

assign out = (addr==00)?d1: 1'bz;
assign out = (addr==01)?d2: 1'bz;
assign out = (addr==10)?d3: 1'bz;
assign out = (addr==11)?d4: 1'bz;

endmodule

例子1修改：

module exe4(out,E1,addr,d1,d2,d3,d4);
input [1:0] addr;
input d1,d2,d3,d4;
input E1;

output out;

assign out = (addr==2'b00)?d1: 1'bz;
assign out = (addr==2'b01)?d2: 1'bz;
assign out = (addr==2'b10)?d3: 1'bz;
assign out = (addr==2'b11)?d4: 1'bz;

endmodule

总结：仔细体会代码，不要图省事！

 

转载于:https://www.cnblogs.com/jianglg3/p/5053411.html