(筆記) 如何使UltraEdit支援VHDL語法顯示? (SOC) (VHDL) (UltraEdit)

Abstract
UltraEdit預設沒有支援VHDL語言，該如何讓UltraEdit顯示出VHDL的語法關鍵字呢?

Introduction
Step 1：
修改wordfile.txt

在C:\Program Files\UltraEdit-32\wordfile.txt加入以下資料

/L15 " VHDL " Line Comment = -- Nocase String Chars =   " File Extensions = VHD VHO
/Delimiters = ; (    )'<>=:+-/*|&
/C1 " VHDL reserved words "
abs access after alias all and architecture array assert attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity signal shared sla sll sra srl subtype
then to transport type
unaffected untis until use
variable
wait when while with
xnor xor
/C2 " VHDL attributes "
active ascending ascending
base
delayed driving driving_value
event
falling_edge
high
image instance_name
last_active last_event last_value left leftof length low
path_name pos pred
quiet
reverse_range right rightof rising_edge
simple_name stable succ
transaction
val value
/C3 " VHDL stings "
"
/C4 " VHDL types "
bit bit_vector boolean
character
integer
line
natural
positive
real
signed std_logic std_logic_vector string
text time
unsigned
/C5 " VHDL Procedures "
endfile
file_close file_open
read readline
write writeline

Conclusion
若你還使用其他語言，可以到http://www.ultraedit.com/downloads/extras.html下載其他語言的wordfile，自行新增到UltraEdit內。