[笔记] 分频计数(七)

 一、Code

module clk_div(
// input 
input clk_50,
input rst_n,
// output
output clk_div
);
/*
// 25分频
reg[5:0] cnt; //2的6次方>50

always@(posedge clk_50 or negedge rst_n)
begin
if(!rst_n)
cnt <= 6'd0;
else if(cnt<6'd49)
cnt <= cnt+1'b1;
else
cnt <= 6'd0;
end

assign clk_div = (cnt <= 6'd24) ? 1'b0 : 1'b1;
*/
/*
// 取20ms,20ns一周期，20ms是十的6次方,即2的20次方
reg[19:0] cnt;

always@(posedge clk_50 or negedge rst_n)
begin
if(!rst_n)
cnt <= 20'd0;
else if(cnt<20'd1_999_999)
cnt <= cnt+20'b1;
else
cnt <= 20'd0;
end

assign clk_div = (cnt <= 20'd499_999) ? 1'b0 : 1'b1;
*/
reg[21:0] cnt; //80ms

always@(posedge clk_50 or negedge rst_n)
begin
if(!rst_n)
cnt <= 22'd0;
else
cnt <= cnt+22'b1;
end

assign clk_div = cnt[21];

endmodule

二、Testbench

initial                                              
	begin                                                  
		clk_50 = 0;
		forever
			#10 clk_50 = ~clk_50;
	end                                                    

initial 
	begin
		rst_n = 0;
		#1000;
		rst_n = 1;
		#5000;
		$stop;
	end                   

转载于:https://www.cnblogs.com/spartan/archive/2011/10/21/2220622.html