IP-XACT IP IEEE交换格式

1 What is  IP-XACT?
      IP-XACT is an XML format that defines and describes electronic components and their designs. IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through tools. The goals of the standard are to ensure delivery of compatible component descriptions from multiple component vendors, to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments), to describe configurable components using metadata, and to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators). Approved as IEEE 1685-2009 on December 9, 2009, published on February 18, 2010.
 
2 有哪工具支持?
Vivado, ARM Socrates etc. 
 
3 IP-XACT就是解决目前在SOC系统设计中的IP集成问题。从图中可以看出IP的支付费用在不断地增长,在SOC设计中占据的比重也越重要。
 
 
参考文献:
1 人物专访:如何解决 IP 集成问题.  https://community.arm.com/cn/b/blog/posts/ip
3 被 Linus Torvalds 批评过的十一种技术.  http://ms.csdn.net/geek/98484
4 AI芯片的架构之争真的有意义吗? https://i-blog.csdnimg.cn/blog_migrate/01666ccf2127a153a3b38ce583394567.png

 

转载于:https://www.cnblogs.com/dpc525/p/7843863.html

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Contents 1. Overview.............................................................................................................................................. 1 1.1 Scope .......................................................................................................................................... 1 1.2 Purpose ....................................................................................................................................... 2 1.3 Design environment ................................................................................................................... 2 1.4 IP-XACT–enabled implementations .......................................................................................... 6 1.5 Conventions used ....................................................................................................................... 7 1.6 Use of color in this standard..................................................................................................... 12 1.7 Contents of this standard .......................................................................................................... 12 2. Normative references......................................................................................................................... 13 3. Definitions, acronyms, and abbreviations.......................................................................................... 15 3.1 Definitions................................................................................................................................ 15 3.2 Acronyms and abbreviations.................................................................................................... 20 4. Interoperability use model ................................................................................................................. 21 4.1 Roles and responsibilities......................................................................................................... 21 4.2 IP-XACT IP exchange flows.................................................................................................... 22 5. Interface definition descriptions ........................................................................................................ 25 5.1 Definition descriptions ............................................................................................................. 25 5.2 Bus definition ........................................................................................................................... 26 5.3 Abstraction definition............................................................................................................... 28 5.4 Ports.......................................................................................................................................... 29 5.5 Wire ports................................................................................................................................. 30 5.6 Qualifiers.................................................................................................................................. 31 5.7 Wire port group ........................................................................................................................ 32 5.8 Wire port mode (and mirrored mode) constraints.................................................................... 33 5.9 Transactional ports ................................................................................................................... 34 5.10 Transactional port group .......................................................................................................... 36 5.11 Extending bus and abstraction definitions ............................................................................... 37 5.12 Clock and reset handling .......................................................................................................... 38 6. Component descriptions .................................................................................................................... 41 6.1 Component ............................................................................................................................... 41 6.2 Interfaces .................................................................................................................................. 43 6.3 Interface interconnections ........................................................................................................ 44 6.4 Complex interface interconnections......................................................................................... 46 6.5 Bus interfaces ........................................................................................................................... 48 6.6 Indirect interfaces..................................................................................................................... 58 6.7 Component channels ................................................................................................................ 59 6.8 Address spaces ......................................................................................................................... 60 6.9 Memory maps........................................................................................................................... 68 6.10 Remapping ............................................................................................................................... 79 6.11 Registers ................................................................................................................................... 81 6.12 Models...................................................................................................................................... 95

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