java上位机编程 网口,uart232串口之一——发送数据到上位机

本程序功能很简单。FPGA发送数据到电脑的串口。因为刚刚学习Verilog，代码并不规范，里面很可能有错误。这里仅仅是记录下，学习的过程。错误的地方，请看到的朋友努力吐槽。

module rs232_tx_cnt(

Clk,

rst_n,

en_go,

tx_done,

sel_bps,

Data,

uart_tx);

input Clk;

input rst_n;

input en_go;

output tx_done;

input [2:0] sel_bps;

input [7:0] Data;

output reg uart_tx;

reg [20:0] Time;

reg [31:0] counter;

reg [3:0] counter2;

wire bps_Start;

reg en;

always @(*) begin

if (sel_bps == 3'd0)

Time <= 5208; //9600

else if (sel_bps == 3'd1)

Time <= 1302; //38400

else if (sel_bps == 3'd2)

Time <= 434; //115200

else

Time <= 5208;

end

always @(posedge Clk or negedge rst_n) begin

if ( rst_n == 1'b0)

en <= 0;

else if (en_go == 1'b1)

en <= 1;

else if (tx_done == 1'b1)

en <= 0;

else

en <= en;

end

reg [7:0] R_Data;

always @(posedge Clk or negedge rst_n) begin

if ( rst_n == 1'b0)

R_Data <= 0;

else if (en_go == 1'b1)

R_Data <= Data;

else

R_Data <= R_Data;

end

//bps产生

always @(posedge Clk or negedge rst_n) begin

if ( rst_n == 1'b0)

counter <= 0;

else if (en == 1'b1)

begin

if (counter == Time - 1)

counter <= 0;

else

counter <= counter + 1'd1;

end

else

counter <= 0;

end

assign bps_Start = ((counter == 0) && (en==1'b1));

always @(posedge Clk or negedge rst_n) begin

if ( rst_n == 1'b0)

counter2 <= 0;

else if( en == 1'b1)

begin

if (tx_done)

counter2 <=0;

else if (counter == Time - 1)

counter2 <= counter2 + 1'b1;

else

counter2 <= counter2;

end

else

counter2 <= 0;

end

assign tx_done = ((counter2 == 9) && (counter == Time - 1));

always @(posedge Clk or negedge rst_n) begin

if (rst_n == 1'b0)

uart_tx <= 1'b1;

else if ( en ==1'b1) begin

case(counter2 )

0: uart_tx <= 1'b0;

1: uart_tx <= R_Data[0];

2: uart_tx <= R_Data[1];

3: uart_tx <= R_Data[2];

4: uart_tx <= R_Data[3];

5: uart_tx <= R_Data[4];

6: uart_tx <= R_Data[5];

7: uart_tx <= R_Data[6];

8: uart_tx <= R_Data[7];

9: uart_tx <= 1'b1;

default : uart_tx <= 1'b1;

endcase

end

else

uart_tx <= 1'b1;

end

endmodule

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

`timescale 1ns/1ps

module top(clk, Rest_n,uart_tx ) ;

input Rest_n;

input clk;

output uart_tx;

reg [7:0] data;

//wire tx_done;

reg en_go;

reg [20:0] cnt;

rs232_tx_cnt u2(

.Clk(clk),

.rst_n(Rest_n),

.en_go(en_go),

.tx_done(),

.sel_bps(3'd2),//

.Data(data),

.uart_tx(uart_tx)

);

always @(posedge clk or negedge Rest_n) begin

if ( Rest_n == 1'b0) begin

en_go <= 0;

data <= 8'h54;

end

else if( cnt == 1) begin

en_go <= 1'b1;

data <=data+1'd1;

end

else en_go <= 1'b0;

end

always @(posedge clk or negedge Rest_n) begin

if ( Rest_n == 1'b0)

cnt <= 0;

//else if( cnt == 50000000 -1) //

else if( cnt == 50000 -1) //for simualato

cnt <= 0;

else

cnt <= cnt + 1'd1;

end

endmodule