&ldb {
status = "okay";
split-mode;
lvds-channel@0 {
reg = <0>;
crtc = "ipu2-di0";
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = ;
timing0: hsd100pxn1 {
clock-frequency = <150000000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <220>;//表示从水平同步信号开始到一行的有效数据开始之间的VCLK的个数
hfront-porch = <40>;//表示一行的有效数据结束到下一个水平同步信号开始之间的VCLK的个数
vback-porch = <21>;//VBPD(vertical back porch):表示在一帧图像开始时,垂直同步信号以后的无效的行数
vfront-porch = <19>;//VFBD(vertical front porch):表示在一帧图像结束后,垂直同步信号以前的无效的行数VSPW
(vertical sync pulse width):表示垂直同步脉冲的宽度,用行数计算
hsync-len = <60>;//HSYNC信号有效时,表示一行数据的开始,信号宽度为(HSPW+ 1)个VCLK信号周期,即(HSPW +1)个无效像素;
HSYNC信号脉冲之后,还要经过(HBPD +1)个VCLK信号周期,有效的像素数据才出现; 随后发出(HOZVAL+ 1)个像素的有效数据;
最后是(HFPD +1)个无效的像素;
vsync-len = <10>;//VSYNC信号有效时,表示一帧数据的开始, 信号宽度为(VSPW +1)个HSYNC信号周期,即(VSPW +1)个无效行;
VSYNC信号脉冲之后,总共还要经过(VBPD+ 1)个HSYNC信号周期,有效的行数据才出现; 所以,在VSYNC信号有效之后,还要经过(VSPW +1 + VBPD + 1)个无效的行;
};
};
};
lvds-channel@1 {
reg = <1>;
crtc = "ipu2-di1";
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
primary;
display-timings {
native-mode = ;
timing1: hsd100pxn1 {
clock-frequency = <150000000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <19>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};2.修改内核代码