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anizationandarchitectureMidtermexam2010/11I.Multi-choice1.Erasureunitforflashmemoryis(B)a.Chiplevelb.bytelevelc.blockleveld.wordlevel2.Cacheusuallyadopts(B)a.essmethod(semisequential)b.essmethodc.essmethodd.readonlymethod3.Ifmemorycycleis250nsand16bitsarereadeachtime,thenthedatatransferrateofthememoryis(d)a.4x106bytes/sb.4Mbytes/sc.8x106bytes/sd.8Mbytes/s4.假设某系统总线在一个总线周期中并行传输4字节信息,一个总线周期占用2个时钟周期,总线时钟频率为10MHz,则总线带宽是(b)a.10MB/sb.20MB/sc.40MB/sd.80MB/s5.浮点数加、减运算过程包括对阶、尾数运算、规格化、舍入和判溢出等步骤。设浮点数的阶码和尾数均采用补码表示,且位数分别为5位和7位(均含2位符号位)。若有两个数X=27x29/32,Y=25x5/8,则用浮点加法计算X+Y的最终结果是(d)a.001111100010b.001110100010c.0**********d.发生溢出6.设某浮点数共12位,其中阶码含1位阶符共4位,以2为底,补码表示;尾数含1位数符共8位,补码表示,规格化。则该浮点数所能表示的最大正数是()。a.27b.28c.28-1d.27-17.不恢复余数除法(也称加减交替除法)Ca.不存在恢复余数的操作b.当某一步运算不够减时,做恢复余数操作c.仅当最后一步余数为负时,做恢复余数操作d.当某一步余数为负时,做恢复余数操作8.指令周期是指(c)a.CPU从主存取出一条指令的时间b.CPU执行一条指令的时间c.CPU从主存取出一条指令加上执行一条指令的时间d.时钟周期时间II.Questions1.Thefollowingfigureshowstherelevantportionofmemoryandprocessorregisters.Pleaseshowtheprogramexecutionfortheinstructionsinmemorylocations1002,1003,and1004.Note:instructionsaretwoaddressesone.“Load$R1,1006”---registerR1?(1006)“Add$R2,$R1”---$R2?($R1)+($R2)“ISZ$R1”---increment$R1,if$R1iszerothenjumpto1005elsedo1004“BR1002”---branch1002MemoryCPU1000Load$R1,1006PC10021001Clear$R21002Add$R2,$R1IR1003ISZ$R11004BR1002R1-51005Store$R2,10071006–5R201007S2.eneratinga16-bitaddressandhavinga16-bitdatabus.a.essdire
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