mrs x2,esr_el1
b bad_mode
ENDPROC(el1_sync)
.align 6
el1_irq:
kernel_entry 1
enable_dbg_if_not_stepping x0
#ifdefCONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_off
#endif
#ifdefCONFIG_PREEMPT
get_thread_info tsk
ldr x24,[tsk, #TI_PREEMPT] // getpreempt count
add x0,x24, #1 // increment it
str x0,[tsk, #TI_PREEMPT]
#endif
irq_handler
#ifdefCONFIG_PREEMPT
str x24,[tsk, #TI_PREEMPT] // restorepreempt count
cbnz x24,1f // preempt count!= 0
ldr x0,[tsk, #TI_FLAGS] // get flags
tbz x0,#TIF_NEED_RESCHED, 1f // needsrescheduling?
bl el1_preempt
1:
#endif
#ifdefCONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_on
#endif
kernel_exit 1
ENDPROC(el1_irq)
#ifdefCONFIG_PREEMPT
el1_preempt:
mov x24,lr
1: enable_dbg
bl preempt_schedule_irq // irq en/disable is done inside
ldr x0,[tsk, #TI_FLAGS] // get newtasks TI_FLAGS
tbnz x0,#TIF_NEED_RESCHED, 1b // needsrescheduling?
ret x24
#endif
/*
* EL0 mode handlers.
*/
.align 6
el0_sync:
kernel_entry 0
mrs x25,esr_el1 // read the syndromeregister
lsr x24,x25, #26 // exceptionclass
cmp x24,#0x15 // SVC in 64-bitstate
b.eq el0_svc
adr lr,ret_from_exception
cmp x24,#0x24 // data abort in EL0
b.eq el0_da
cmp x24,#0x20 // instruction abortin EL0
b.eq el0_ia
cmp x24,#0x07 // FP/ASIMD access
b.eq el0_fpsimd_acc
cmp x24,#0x2c // FP/ASIMDexception
b.eq el0_fpsimd_exc
cmp x24,#0x18 // configurable trap
b.eq el0_undef
cmp x24,#0x26 // stack alignmentexception
b.eq el0_sp_pc
cmp x24,#0x22 // pc alignmentexception
b.eq el0_sp_pc
cmp x24,#0x00 // unknown exceptionin EL0
b.eq el0_undef
cmp x24,#0x30 // debug exceptionin EL0
b.ge el0_dbg
b el0_inv
#ifdefCONFIG_COMPAT
.align 6
el0_sync_compat:
kernel_entry 0, 32
mrs x25,esr_el1 // read the syndromeregister
lsr x24,x25, #26 // exceptionclass
cmp x24,#0x11 // SVC in 32-bitstate
b.eq el0_svc_compat
adr lr,ret_from_exception
cmp x24,#0x24 // data abort in EL0
b.eq el0_da
cmp x24,#0x20 // instruction abortin EL0
b.eq el0_ia
cmp x24,#0x07 // FP/ASIMD access
b.eq el0_fpsimd_acc
cmp x24,#0x28 // FP/ASIMDexception
b.eq el0_fpsimd_exc
cmp x24,#0x00 // unknown exceptionin EL0
b.eq el0_undef
cmp x24,#0x30 // debug exceptionin EL0
b.ge el0_dbg
b el0_inv
el0_svc_compat:
/*
*AArch32 syscall handling
*/
adr stbl,compat_sys_call_table // load compatsyscall table pointer
uxtw scno,w7 // syscall numberin w7 (r7)
mov sc_nr, #__NR_compat_syscalls
b el0_svc_naked
.align 6
el0_irq_compat:
kernel_entry 0, 32
b el0_irq_naked
#endif
el0_da:
/*
*Data abort handling
*/
mrs x0,far_el1
disable_step x1
isb
enable_dbg
// enable interrupts before calling themain handler
enable_irq
mov x1,x25
mov x2,sp
b do_mem_abort
el0_ia:
/*
*Instruction abort handling
*/
mrs x0,far_el1
disable_step x1
isb
enable_dbg
// enable interrupts before calling themain handler
enable_irq
orr x1,x25, #1 << 24 // usereserved ISS bit for instruction aborts
mov x2,sp
b do_mem_abort
el0_fpsimd_acc:
/*
*Floating Point or Advanced SIMD access
*/
mov x0,x25
mov x1,sp
b do_fpsimd_acc
el0_fpsimd_exc:
/*
*Floating Point or Advanced SIMD exception
*/
mov x0,x25
mov x1,sp
b do_fpsimd_exc
el0_sp_pc:
/*
*Stack or PC alignment exception handling
*/
mrs x0,far_el1
disable_step x1
isb
enable_dbg
// enable interrupts before calling themain handler
enable_irq
mov x1,x25
mov x2,sp
b do_sp_pc_abort
el0_undef:
/*
*Undefined instruction
*/
mov x0,sp
b do_undefinstr
el0_dbg:
/*
*Debug exception handling
*/
tbnz x24,#0, el0_inv // EL0 only
mrs x0,far_el1
disable_step x1
mov x1,x25
mov x2,sp
b do_debug_exception
el0_inv:
mov x0,sp
mov x1,#BAD_SYNC
mrs x2,esr_el1
b bad_mode
ENDPROC(el0_sync)
.align 6
el0_irq:
kernel_entry 0
el0_irq_naked:
disable_step x1
isb
enable_dbg
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