计算机原理WR是什么,计算机原理

4.3 4.4 4.5 4.6 4.1 4.2

(ALU)

CPU

PC IR IDALU XR CU

1) (1) CPU (2) (3) (4)

2) (1) PC CPU (2) MAR MBR IR PSW PC MARMMBRIR CPU

/

4.1

4.1

4.1

PC

PC +1

HALT

BRANCH

PC

RISC432864CISCRISC

4.1

4.1.1 88AC811

4.1.1 (a)1 (b)1

765

43210

op

address

765432

10

op

address

4.1.1 525=32 SP 00011111B11

4.1.1 8

4.1.1 ?4.1

4.1.2ADD

AC:=AC + Memory(address) 1

765

43210

000

address

4.1.2SUB

AC:=AC - Memory(address) 1

765

43210

001

address

4.1.2STORE

Memory(address):=AC 1

765

43210

010

address

4.1.2LOAD

AC := Memoryaddress 1

765

43210

011

address

4.1.2BRANCH

IF (AC(7)==1)THEN PC:=addressELSE PC:=PC+1END IF1

765

43210

100

address

4.1.2CALL

SP := SP 1MemorySP := PCPC := address1

765

43210

101

address

4.1.2RETURN

PC := MemorySPSP := SP + 1

0

765432

10

111001

((

4.1.2ACCLEARAC

ACAC:= 0 0

765432

10

111000

((

4.1.2SHIFTR

again:while counter/='00' loopAC (0:6):=AC(1:7)AC(7):=0counter:=counter-1end loop again 1

765432

10

111101

counter

4.1.2

again:while counter/='00' loopAC(1:7):=AC(0:6)AC(0):=0counter:=counter-1end loop again1

765432

10

111110

counter

4.2

4.2

4.2

4.2.1

4.2.1

4.2.1PCPC()

4.2.11PC234PC+IFEX1234

NOPADD mem MUL mem4.2.1

4.2.1

4.2.1

4.2.1

CPU CPU4 CPU 44.2.1

1) CUMARPC4.2.1

4.2.12)

4.2.13) 4)

4.2.1

4.2.1

4.2.1PCPCIRIRMAR

4.2.1MBRRWMBR

4.2.1IF IFIF1EXEXEX0

4.2.1

4.2.1PC 0PC1 PC1PCMBRIRMBRIR

4.2.1PCMAR PCMARIRMARIRMAR

4.2.1RR RRRWW WR

4.2.1IFIF IFIFIFEXEX EXIF

4.2.1

4.2.1ACA0ALUACALUACALUALUACMBRAC MBRMBRACMBRAC

4.2.2 ?

4.2.2

4.2.2

CU CPU 4.2.2

1. (1) (2) (4) (3) CU CU INTR HRQ 4.2.2

2. (1) CPU (2) INTAHLDA IO/ 4.2.2

4.2.2

a[1]:2020

a[0]:2016

b[1]:2012

b[0]:2008

c[1]:2004

c[0]:2000

LOAD

ADD

STORE

LOAD

ADD

STORE

JUMP

NEXT: 200

20

16

12

8

4

0

24

SHL

SHL

28

32

PCIRACCUALU ADD @ X PCIRCU4.2.2

ADD @ X 4.2.2

ADD @ X ALU4.2.2AC

Micro-OPOP104.2.2

4.2.2

1 4.2.2

14.2.2

i

3

2

CLOCK

1

2 4.2.2nn

24.2.2

3

2

(3)

2

1

1

1

(2)

4.2.2

14.2.2

CLKT0T1T2T3

CLK

2

34.2.2

4.2.2 3

(IF)

(EX)

T0

T1

T2

T3

T0

T1

T2

T3

T0PC

T0

T1

T1

T2PC+1

T2

T3

T3

4tdn(78ns/m)()4.2.2

4Tcpntd+=(1/3~1/4)ntd

4.2.2

8.52678ns:n=8.5+2+6+7=23.5()td=8ns=1/3(ntd)=62nsTcpntd+=23.58+62=250ns250ns4MHz4.2.2

4.2.3 ALU

MAR

MBR

RW

PC

IR

AC

4.2.3

4.2.3 1)

2) CLKT0T1T2T3

4.2.3 3)

4.2.3 T0T1T2T33)

CLEART0T1T2T34.2.3 3)

4.2.3 ADD xPCMAR MBRIR IRMAR PC1PC AC PC IR ALUAC 3) ADD

ALU

(6)

+1

3) ADD4.2.3

ALU

(6)

+4

=1

=1

1

=1

=1

1

2

=1

(6)=1

3) ADD4.2.3

ALU

(6)

+1

3) ADD4.2.3

=1

=1

1

IR

2

=1

=1

3

4

=1

=1

=1

=1

(6)=1

3) ADD4.2.3

T0IRMARMBR =1MBR =1T1(6)=1T2ALUMBRAC =1ALUT3

T3ALUAC =1ACEX,IF=1=1

ALU

(6)

+1

4.2.3 3) ADD

=1

=1

1

2

=1

(6)=1

=1

=1

=1

3

4

(6)=1

=1

5

6

=1

=1

7

=1

8

=1

=1

4)4.2 ADD

4.3 SUBTRACT

4.4 STORE

4.5 LOAD

4.6 CLEAR

4.7 5

4.2.3 (1)IF = EX (2)IF = IF (3)EX= IF (4)EX=EX (5)R=IFT0+EXT0 (ADD+SUB+LOAD) (6)R=IFT1+EXT1 (ADD+SUB+LOAD) (7)W=EXT0STORE (8 W=EXT1STORE 5)

4.2.3 (9) PC1=IFT2 (10) PCMAR=IFT0 (11) MBRIR=IFT1 (12)IRMAR=EXT0(ADD+SUB+STORE+LOAD) (13) =EXT2ADD (14) =EXT2SUB (15) ALUACC=EXT3 (ADD+SUB) (16) AC=EXT3CLEAR (17) ACMBR=EXT0STORE (18MBRAC=EXT3LOAD

4.2.3 6) /

4.2.3 6

3/8

000 = ADD

010 = STORE

011 = LOAD

001 = SUBTRACT

OP0

OP1

OP2

4.11

3/8

111000 = CLEAR

111010

111011

111001 = RETURN

OP3

OP4

OP5

111

100 = BRANCH

111101 = SHIFTR

111110 = SHIFTL

111111

101 = CALL

110

111100

4.2.3 (15) ALUAC(15)=EXT3ADD+SUB

4.3

4.3

4.3.1PCPC + 1

PCnCPUPC1

4.3.1

IF (AC(7)==1)THEN PC:=addressELSE PC:=PC+1END IF

765

43210

100

address

4.8 BRANCH

4.3.1(19) IRPC = EXT2BRANCH(AC7=1)PCPC1IRPCPC

4.3.1CALLSP := SP 1MemorySP := PCPC := address

765

43210

101

address

SPIRCUPCPCSP4.3.1

4.9 CALL

4.3.1PC := MemorySPSP := SP + 1

765432

10

111001

x x

4.10 RETURN

4.3.1(20)SPMAR=EXT0CALL+RETURN(21)SP1=EXT1RETURN(22)SP1=IFT3CALL(23)PCMBR=EXT0CALL(24)MBRPC=EXT2RETURN

4.3.1(5) R = IF T0 + EX T0 (ADD + SUB): R=IF T0 + EXT0 (ADD + SUB + RETURN)(6) R = IF T1 + EX T1 (ADD + SUB+LOAD)R= IFT1 + EXT1 (ADD + SUB +LOAD + RETURN)(7) W = EX T0 STOREW = EXT0 (STORE + CALL)

4.3.1(8) W = EX T1 STOREW = EX T1 STORE + CALL(18) IRPC = EXT2AC7 = 1 BRANCHIRPC = EX T2 ((AC7 = 1) BRANCH + CALL T

4.3.2

4.3.2

4.3.2

4.3.2

4.3.2

4.3.2

4.14 LTSG

4.14 LTSG

4.14

4.3.22SCIR1IR0SC1SC0SC1SC0&IRSCLTSGSR11&4.15 SRSR

4.3.2SRIFT3SRSRSC=00SREX

4.11 SHIFTR

4.3.2(25)IRSC=IFT3(SHIFTR+ SHIFTL)(26)SR=IFT3(SHIFTR+ SHIFTL)(27)SR=SRTLi(SC=00) (SHIFTR+ SHIFTL)(28)=SRTLi (SC00) SHIFTR(29)=SRTLi (SC00) SHIFTL(3) EX=IFT3(ADD+SUBTRACT+STORE+LOAD+CLEAR+BRANCH+CALL+RETURN)+SRTLi(SC=00) (SHIFTR+ SHIFTL)

4.3.2

4.3.2

4.4

4.4Wilkes

OnTv 1 2 OnTvOnTv 4.4

4.4.1n10n

0

1

2

n-2

n-1

PC

PC+1

IRPC

4.4.1

4.4.1CPUCPU

4.4.1(CM)M

4.4.1

4.4.1

CMAR CPU

4.4.1

4.4.1

4.4.1

4.4.1emulation

1951Wilkes1953Wilkes 1965IBM 3604.4.2 Wilkes

1965IBM 360IBM system/3604.4.2 Wilkes

WilkesCMARFCMARIR SCM

WilkesCMIRCMARFCMARS4.4.2 Wilkes

CMK~M 4.4.2 Wilkes

IR4.4.2 Wilkes

CMARAR4.4.2 Wilkes

FCMAR 4.4.2 Wilkes

SCMARCMIR4.4.2 Wilkes

Wilkes

CMARFCMARIR

SCM uIR

WilkesCMIRFCMARFCMARCMARCMIRFCMAR4.4.2 Wilkes

(1) CMBR N + 1 CMBR CMBR N + 2

(2) CMBR CMBR CMBR LOAD P + 1 P + 2 N

(2) CMBR CMBR CMBR ADD Q + 1 Q + 2 NADD Q + 3 CMBR

VS. VS. 4.4.2 Wilkes

4.4.2 Wilkes VS. VS.

4.4.2 Wilkes VS. RISCCISC

4.4.3ALUAC+MBRALUACC-MBR4.13

1

4.4.32

4.4.31(1) (2) (3) 21 26 40 6 26 6 32

4.4.32

1

2

3

25

26

27

31

32

4.4.3

14.23

4.4.34.24

CM

FCMAR

MAP(IR)

IR

FCMAR(0

FCMAR(CM()

FCMAR(FCMAR+MAP(IR)

4.4.34.17 MAPIR

IR ADD CLEAR SUB STORE LOADMAP(IR) 1