verilog+case与C语言,用Verilog语言设计一个3-8译码器~(要求分别用case语句和if_case语句各写一份~)...

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风筝有风FZYF

2013.09.10

采纳率：53%    等级：12

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module decoder38(

input [2:0]code,

output reg[7:0]result

);

always@(*)

begin

case(code)

3'b000: result = 8'h01;

3'b001: result = 8'h02;

3'b010: result = 8'h04;

3'b011: result = 8'h08;

3'b100: result = 8'h10;

3'b101: result = 8'h20;

3'b110: result = 8'h40;

3'b111: result = 8'h80;

endcase

end

endmodule

module decoder38(

input [2:0]code,

output reg[7:0]result

);

always@(*)

begin

if(code[2])

if(code[1])

if(code[0])

result = 8'h80;

else

result = 8'h40;

else

if(code[0])

result = 8'h20;

else

result = 8'h10;

else

else

if(code[1])

if(code[0])

result = 8'h08;

else

result = 8'h04;

else

if(code[0])

result = 8'h02;

else

result = 8'h01;

else

end

endmodule

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