胡瑜 简介中科院计算机所,专家人才库数据----中国科学院计算技术研究所

期刊文章:

[1] Jing Ye, Qingli Guo, Yu Hu, Xiaowei Li, "Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted, 2018

[2] Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Weipin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles Liu, Sam Pan, "Diagnosis and Layout Aware (DLA) Scan Chain Stitching," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 466-479, 2015

[3] Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang, "Diagnose Failures Caused by Multiple Locations At-a-Time," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 824-837, 2014

[4] Yu Hu, Jing Ye, Zhiping Shi, Xiaowei Li, "LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization," IEICE Transactions on Information and Systems (TIS), pp. 323-331, 2017

[5] Weina Lu, Yu Hu, Jing Ye, Xiaowei Li, "Going Cooler with Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 2525-2537, 2017

[6] Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang, "Fault Tolerance On-Chip: A Reliable Computing Paradigm Using Self-test, Self-diagnosis, and Self-repair (3S) Approach," Science China Information Sciences (SCIS), pp. 1-17, 2017

[7] Bing Li, Yu Hu, Ying Wang, Jing Ye, Xiaowei Li, "Power-Utility-Driven Write Management for MLC PCM," ACM Journal on Emerging Technologies in Computing Systems (JETC), pp. 50:1-50:22, 2017

专利：

[1] 叶靖，胡瑜，郭青丽，龚越，李晓维，“模糊输入输出的强物理不可克隆函数，”中国，ZL201610134261.1，2018-8-28

[2] 叶靖，胡瑜，李晓维，“一种CPU+FPGA集成芯片的强PUF认证方法及系统，”中国，ZL201610082885.3，2018-5-31

[3] 叶靖，胡瑜，李晓维，“一种集成电路故障诊断系统及方法，”中国，ZL200910237064.2，2011-11-16

[4] 李晓维，胡瑜，叶靖，“一种高稳定性的强物理不可克隆函数电路及其设计方法，”中国，ZL201610074180.7，2018-5-31

[5] 黄柯衡，叶靖，胡瑜，李晓维，“一种适用于FPGA的可靠性评估方法和装置，”中国，ZL201310594897.0，2017-4-12

[6] Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine, Martin Keim, Ronald Press, Jing Ye, Yu Hu, "Test Access Architecture for Stacked Memory and Logic Dies," United States, US9689918B1, 2017-6-27

[7] Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Jing Ye, Yu Hu, "Test Architecture for Characterizing Interconnects in Stacked Designs," United States, US9335376B2, 2016-5-10