linux arm64 串口调试,AARCH64 串口调试

// 1. 目录

Makefile

build_version.c

head.S

map.lds.S

// 2. Makefile

CROSS_COMPILE ?= aarch64-linux-

CC          := $(CROSS_COMPILE)gcc

LD          := $(CROSS_COMPILE)ld

OBJCOPY     := $(CROSS_COMPILE)objcopy

TARGET  := vmlinux

LINKER_SCRIPT   := map.lds

BINSUFFIX := .bin

CFLAGS  := -nostdinc -nostdlib

LDFLAGS := -nostdinc -nostdlib

all: map.lds

$(CC) -c $(CFLAGS) build_version.c

$(CC) -c $(CFLAGS) head.S

$(LD) $(LDFLAGS) head.o build_version.o -o $(TARGET) -T$(LINKER_SCRIPT)

$(OBJCOPY) -O binary $(TARGET) $(TARGET)$(BINSUFFIX)

map.lds: map.lds.S

$(CC) -E -DCONFIG_VENDOR_TEXT=0x4008000 -P $< > $@

# -E  -D__KERNEL__ -mlittle-endian -DTEXT_OFFSET=0x00080000 -P -C -Uarm64 -D__ASSEMBLY__ -DLINKER_SCRIPT

clean:

@rm -f $(LINKER_SCRIPT) $(TARGET) $(TARGET)$(BINSUFFIX)

@rm -f *.o

# map.lds: Makefile

# head.S: Makefile

// 3. map.lds.S

// #define CONFIG_VENDOR_TEXT      0x4008000

/*

* DDR Layout:

*            0x100_0000, 0x7F00_0000

*/

OUTPUT_ARCH(aarch64)

ENTRY(stext)

SECTIONS

{

. = CONFIG_VENDOR_TEXT;

.text : {

stext = .;

*(.text)

}

.rodata : {

*(.rodata)

}

.data : {

*(.data)

}

.bss : {

*(.bss)

}

/DISCARD/ : {

}

}

// 4. build_version.c

const char *__build_version = "vmlinux built On "__DATE__ ", " __TIME__ "\r\n";

// 5. head.S

#define CONFIG_VENDOR_PL011_CONSOLE_BASE 0xBF800000

.macro  lock, LK

.endm

.macro  unlock, LK

.endm

.macro  __puthex, val, str

MOV   X23, \val

MOV   X0, \str

BL    puts

MOV   X0, X23

LDR   X1, =__str_align_buf

BL  __tohexstr_align

LDR   X0, =__str_align_buf

BL  puts

MOV   X0, #'\r'

BL  __putc

MOV   X0, #'\n'

BL  __putc

.endm

.extern __build_version

.text

reset:

/* Initialize PL011 UART, by polling */

NOP

BL  pl011_hw_init

LDR   X0, __build_version

BL    puts

/* TEST */

LDR   X0, =__str_tmp_buf

LDR   X1, =__str_hello_world

__puthex X0, X1

MOV   X27, #0

loop:

ADD   X27, X27, #1

AND   X27, X27, 0x03F

LDR   X0, =__str_tmp_buf

ADD   X0, X0, X27

MOV   X19, X0

MOV   X0, X19

LDR   X1, =__str_offset

__puthex X0, X1

MOV   X0, X19

MOV   X1, X19

BL    __tohexstr

ADD   X0, X19, #16

MOV   X2, #'\r'

STRB  W2, [X0], #1

MOV   X2, #'\n'

STRB  W2, [X0], #1

STRB  WZR,[X0]

MOV   X0, X19

BL    puts

/* */

BL  __delay

B   loop

die:  B   die

.align 3

__str_hello_world:

.asciz   "Start Address : "

__str_offset:

.asciz   "offset : "

.align 3

.data

.align 3

__str_align_buf:

.space 32

__str_tmp_buf:

.space 256

.text

.align 3

#define PL01XA  X3

#define PL01XV  W2

.global __tohexstr

__tohexstr:

MOV   X21, X30

ANDS  X2, X1, 0x7

BEQ   __tohexstr_align

MOV   X29, X1

/*

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

STRB  WZR, [X1], #1

*/

STRB  WZR, [X1]

LDR   X1, =__str_align_buf

BL    __tohexstr_align

MOV   X0, X29

LDR   X1, =__str_align_buf

LDP   X2, X3, [X1]

/* DEBUG

MOV   X16, X2

MOV   X17, X3

MOV   X18, X0

MOV   X0, X3

LDR   X1, =__str_align_buf

BL    __tohexstr_align

LDR   X0, =__str_align_buf

BL    puts

MOV   X3, X16

MOV   X0, X3

LDR   X1, =__str_align_buf

BL    __tohexstr_align

LDR   X0, =__str_align_buf

BL    puts

MOV   X2, X16

MOV   X3, X17

MOV   X0, X18

*/

/* Direct Write Byte

*

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  WZR, [X0]

RET   X21

*/

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W2, [X0], #0x1

LSR   X2, X2, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  W3, [X0], #0x1

LSR   X3, X3, #8

STRB  WZR, [X0]

RET   X21

/* BUG() ?!!!

*

MOV   X4, #8

1:STRB  W3, [X0], #0x1

LSR   X3, X3, #8

SUBS  X4, X4, #1

BCS   1b

MOV   X4, #8

3:STRB  W2, [X0], #0x1

NOP

LSR   X2, X2, #8

SUBS  X4, X4, #1

BCS   3b

4:STRB  WZR,[X0]

RET   X21

*/

.global __tohexstr_align

__tohexstr_align:

MOV   X7, X1

MOV   X5, XZR

MOV   X6, XZR

MOV   X1, #0x0F

MOV   X8, #7

MOV   X12,#64

1:CMP   X1, #0

BEQ   4f

AND   X2, X0, X1

CLZ   X3, X1

ADD   X11, X3, #4

SUB   X11, X12, X11

LSR   X3, X3, #2

LSR   X2, X2, X11

CMP   X2, #9

BHI   5f

ADD   X2, X2, #0x30

B     6f

5:SUB   X2, X2, #10

ADD   X2, X2, #0x41

6:CMP   X3, #8

BLO   2f

SUB   X3, X3, #8

SUB   X3, X8, X3 /* RSB   X3, X3, #7 */

LSL   X3, X3, #3

LSL   X2, X2, X3

ADD   X6, X6, X2

B     3f

2:SUB   X3, X8, X3 /* RSB   X3, X3, #7 */

LSL   X3, X3, #3

LSL   X2, X2, X3

ADD   X5, X5, X2

3:BIC   X0, X0, X1

LSL   X1, X1, #4

B     1b

4:REV   X5, X5

REV   X6, X6

STP   X5, X6, [X7], #16

STRB  WZR, [X7]

RET

.global __putc

__putc:

B   pl011_hw_putc

.global __getc

__getc:

B   pl011_hw_getc

.global puts

puts:

MOV   X29, X30

MOV   X28, X0

1:LDRB  W0, [X28], #1

# LDRB  W0, [X28]

# ADD   X28, X28, #1

CMP   W0, #0

BEQ   2f

BL    __putc

B     1b

2:RET   X29

pl011_hw_getc:

LDR     PL01XA, =CONFIG_VENDOR_PL011_CONSOLE_BASE

1:LDR     PL01XV, [PL01XA, 0x18]

ANDS    PL01XV, PL01XV, 0x10

bne     1b

LDR     PL01XV, [PL01XA]

ANDS    W0, PL01XV, 0x0FF

RET

pl011_hw_putc:

LDR     PL01XA, =CONFIG_VENDOR_PL011_CONSOLE_BASE

1:LDR     PL01XV, [PL01XA, 0x18]

ANDS    PL01XV, PL01XV, 0x20

bne     1b

STRB    W0, [PL01XA]

RET

pl011_hw_init:

LDR     PL01XA, =CONFIG_VENDOR_PL011_CONSOLE_BASE

STR     WZR, [PL01XA, 0x30]

DSB     ST

MOV     PL01XV, 0x28

STR     PL01XV, [PL01XA, 0x24]

DSB     ST

MOV     PL01XV, 0x2C

STR     PL01XV, [PL01XA, 0x28]

DSB     ST

MOV     PL01XV, 0x70

STR     PL01XV, [PL01XA, 0x2C]

DSB     ST

MOV     PL01XV, 0x301

STR     PL01XV, [PL01XA, 0x30]

DSB     ST

RET

__delay:

LDR     X0, =0x1000000

1:SUBS    X0, X0, 1

BNE     1b

RET

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