HI-3584
Enhanced ARINC 429
3.3V Serial Transmitter and Dual Receiver
PIN CONFIGURATIONS(Top View)
(See page 13 for additional pin configuration)
GENERAL DESCRIPTION
The HI-3584 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584 design offers many
enhancements to the industry standard HI-8282
architecture. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584’s status
register.
Other new features include a programmable option of data
or parity in the 32nd bit, and the ability to unscramble the 32
bit word. Also, versions are available with different values
of input resistance to allow users to more easily add
external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3584 applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
.
Additional interface circuitry such as the Holt HI-8585 or
HI-8586 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
APPLICATIONS
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Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS3584 Rev. E)
/06
09
September 2006
FEATURES
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ARINC specification 429 compatible
Dual receiver and transmitter interface
Programmable label recognition
32 x 32 FIFOs each receiver and transmitter
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & full military temperature ranges
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3.3V logic supply operation
Analog line receivers connect directly to ARINC bus
On-chip 16 label memory for each receiver
Independent data rate selection for transmitter
and each receiver
HI-3584PQI
&
HI-3584PQT
39 - N/C
38 -
37 - ENTX
36 - N/C
35 -
34 - 429DO
33 - N/C
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00
CWSTR
FFT
HFT
PL2
PL1
429DO
FF1
HF1
D/R2
FF2
HF2
EN1
EN2
-1
-2
-3
-4
-5
SEL - 6
-7
-8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
52 - Pin Plastic Quad Flat Pack (PQFP)
48
47
46 -
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41
40 -
39 -
38 - TX/R
37 -
36 -
35 -
34 - BD01
-
- ENTX
- 429DO
BD00
33 - N/C
CWSTR
429DO
FFT
HFT
PL2
PL1
N/C - 1
-2
-3
-4
-5
-6
-7
SEL - 8
-9
-10
N/C - 11
BD15 - 12
D/R1
FF1
D/R2
FF2
HF2
EN1
EN2
HF1
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
(Note: All 3 VDD pins
be connected to the same 3.3V supply)
must
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
HI-3584PCI
&
HI-3584PCT
See Note below