matlab test bench,Verilog 仿真文件testbench编写样例

`timescale 1ns/100ps

module testbench;

localparam DATA_WIDTH = 32;

localparam CLK_100_PERIOD = 5;

localparam CLK_200_PERIOD = 2.5;

localparam SIM_TIME = 150000;

localparam ;

localparam ;

reg clk_100, clk_200;

wire clk;

assign clk = clk_100;

always

begin

clk_100 = 0;

forever #CLK_100_PERIOD clk_100 = ~clk_100;

end

always

begin

clk_200 = 0;

forever #CLK_200_PERIOD clk_200 = ~clk_200;

end

reg rstn;

integer fp_testin;

integer fp_matlab_out;

integer fp_sim_out;

integer fp_outdiff;

reg signed [DATA_WIDTH/2-1:0] matlab_in_re,   matlab_in_im;

reg signed [DATA_WIDTH/2-1:0] matlab_out_re,  matlab_out_im;

reg signed [DATA_WIDTH/2-1:0] matlab_diff_re, matlab_diff_im;