linux内核打开一个文件的全过程,linux内核启动内核解压过程分析

#include /* working in physical space... */

#undef S3C2410_WDOGREG

#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))

/* how many bytes we allow into the FIFO at a time in FIFO mode */

#define FIFO_MAX     (14)

#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)

static __inline__ void

uart_wr(unsigned int reg, unsigned int val)

{

volatile unsigned int *ptr;

ptr = (volatile unsigned int *)(reg + uart_base);

*ptr = val;

}

static __inline__ unsigned int

uart_rd(unsigned int reg)

{

volatile unsigned int *ptr;

ptr = (volatile unsigned int *)(reg + uart_base);

return *ptr;

}

/* we can deal with the case the UARTs are being run

* in FIFO mode, so that we don't hold up our execution

* waiting for tx to happen...

*/

static void putc(int ch)

{

if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {

int level;

while (1) {

level = uart_rd(S3C2410_UFSTAT);

level &= fifo_mask;

if (level < fifo_max)

break;

}

} else {

/* not using fifos */

while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)

barrier();

}

/* write byte to transmission register */

uart_wr(S3C2410_UTXH, ch);

}

static inline void flush(void)

{

}

#define __raw_writel(d, ad)            \

do {                            \

*((volatile unsigned int __force *)(ad)) = (d); \

} while (0)

/* CONFIG_S3C_BOOT_WATCHDOG

*

* Simple boot-time watchdog setup, to reboot the system if there is

* any problem with the boot process

*/

#ifdef CONFIG_S3C_BOOT_WATCHDOG

#define WDOG_COUNT (0xff00)

static inline void arch_decomp_wdog(void)

{

__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

}

static void arch_decomp_wdog_start(void)

{

__raw_writel(WDOG_COUNT, S3C2410_WTDAT);

__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);

}

#else

#define arch_decomp_wdog_start()

#define arch_decomp_wdog()

#endif

#ifdef CONFIG_S3C_BOOT_ERROR_RESET

static void arch_decomp_error(const char *x)

{

putstr("\n\n");

putstr(x);

putstr("\n\n -- System resetting\n");

__raw_writel(0x4000, S3C2410_WTDAT);

__raw_writel(0x4000, S3C2410_WTCNT);

__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);

while(1);

}

#define arch_error arch_decomp_error

#endif

#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO

static inline void arch_enable_uart_fifo(void)

{

u32 fifocon = uart_rd(S3C2410_UFCON);

if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {

fifocon |= S3C2410_UFCON_RESETBOTH;

uart_wr(S3C2410_UFCON, fifocon);

/* wait for fifo reset to complete */

while (1) {

fifocon = uart_rd(S3C2410_UFCON);

if (!(fifocon & S3C2410_UFCON_RESETBOTH))

break;

}

}

}

#else

#define arch_enable_uart_fifo() do { } while(0)

#endif

static void

arch_decomp_setup(void)

{

/* we may need to setup the uart(s) here if we are not running

* on an BAST... the BAST will have left the uarts configured

* after calling linux.

*/

arch_detect_cpu();

arch_decomp_wdog_start();

/* Enable the UART FIFOs if they where not enabled and our

* configuration says we should turn them on.

*/

arch_enable_uart_fifo();

}

arch/arm/mach-s3c2410/include/mach/uncompress.h

static inline int is_arm926(void)

{

unsigned int cpuid;

asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));

return ((cpuid & 0xff0) == 0x260);

}

static void arch_detect_cpu(void)

{

unsigned int cpuid;

cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);

cpuid &= S3C2410_GSTATUS1_IDMASK;

if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||

cpuid == S3C2410_GSTATUS1_2442 ||

cpuid == S3C2410_GSTATUS1_2416 ||

cpuid == S3C2410_GSTATUS1_2450) {

fifo_mask = S3C2440_UFSTAT_TXMASK;

fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;

} else {

fifo_mask = S3C2410_UFSTAT_TXMASK;

fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;

}

}