19-4794; Rev 0; 11/98
EVAALVUAAILTAIOBNLEKIT +5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
General Description Features MAX1205
The MAX1205 is a 14-bit, monolithic, analog-to-digital o Monolithic, 14-Bit, 1Msps ADC
converter (ADC) capable of conversion rates up to o +5V Single Supply
1Msps. This integrated circuit, built on a CMOS pro-
cess, uses a fully differential, pipelined architecture o SNR of 80dB for fIN = 500kHz
with digital error correction and a short self-calibration o
procedure that corrects for capacitor and gain mis- SFDR of 87dB for fIN = 500kHz
matches and ensures 14-bit linearity at full sample o Low Power Dissipation: 257mW
rates. An on-chip track/hold (T/H) maintains superb o
dynamic performance up to the Nyquist frequency. The On-Demand Self-Calibration
MAX1205 operates from a single +5V supply. o Differential Nonlinearity Error: ±0.3LSB
The fully differential inputs allow an input swing of o Integral Nonlinearity Error: ±1.2LSB
±VREF. The reference is also differential, with the posi-
tive reference (RFPF) typically connected to +4.096V o Three-State, Two’s Complement Output Data
and the negative reference (RFNF) connected to ana-
log ground. Additional sensing pins (RFPS, RFNS) are
provided to compensate for any resistive-divider action Ordering Information
that may occur due to finite internal and external resis-
tances in the reference traces and the on-chip resis- PART TEMP. RANGE PIN-PACKAGE
tance of the reference pins. A single-ended input is MAX1205CMH 0°C to +70°C 44 MQFP
also possible using two operational amplifiers. MAX1205EMH -40°C to +85°C 44 MQFP
The power dissipation is typically 257mW at +5V, at a
sampling rate of 1Msps. The device employs a CMOS-
compatible, 14-bit parallel, two’s complement output
data format. For higher sampling rates, the MAX1201 is
a 2.2Msps pin-compatible upgrade to the MAX1205. Pin Configuration
The MAX1205 is available in an MQFP package, and
operates over the commercial (0°C to +70°C) and the TOP VIEW
extended (-40°C to +85°C) temperature ranges. END_CAL
INN N.C. N.C. INP RFNS RFNF RFPS RFPF CM TEST0
Applications 44 43 42 41 40 39 38 37 36 35 34
Imaging
Communications ST_CAL 1 33 OE
AGND 2 32 DAV
Medical AVDD 3 31 CLK
AGND 4 30 DVDD
Scanners AGND 5 29 DGND
Data Acquisition AVDD 6 MAX1205 28 DGND
DOR 7 27 DVDD
D13 8 26 TEST1
D12 9 25 TEST2
D11 10 24 TEST3
D10 11 23 D0
12 13 14 15 16 17 18 19 20 21 22
D9 D8 D7 D6 DRVDD DGND D5 D4 D3 D2 D1
MQFP
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
MAX1205 ABSOLUTE MAXIMUM RATINGS
AVDD to AGND, DGND ..........................................................+7V Continuous Power Dissipation (TA = +70°C)
DVDD to DGND, AGND..........................................................+7V 44-Pin MQFP (derate 11.11mW/°C above +70°C)........889mW
DRVDD to DGND, AGND .......................................................+7V Operating Temperature Ranges (TA)
INP, INN, RFPF, RFPS, RFNF, RFNS, MAX1205CMH .....................................................0°C to +70°C
CLK, CM.................................(AGND - 0.3V) to (AVDD + 0.3V) MAX1205EMH ..................................................-40°C to +85°C
Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Storage Temperature Range .............................-65°C to +150°C
Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Lead Temperature (soldering, 10sec) .............................+300°C
Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz,
digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range VIN Single-ended 4.096 4.5 V
(Notes 2, 3) Differential ±4.096 ±4.5
Input Resistance (Note 4) RI 55 kΩ
Input Capacitance (Note 3) CI Per side in track mode 21 pF
REFERENCE/EXTERNAL
Reference Voltage (Note 3) VREF 4.096 4.5 V
Reference Input Resistance 700 1000 Ω
TRANSFER CHARACTERISTICS
Resolution (no missing codes) RES After calibration, guaranteed 14 Bits
(Note 5)
Integral Nonlinearity INL ±1.2 LSB
Differential Nonlinearity DNL -1 ±0.3 +1 LSB
Offset Error -0.2 ±0.003 +0.2 %FSR
Gain Error -5 -3.0 +5 %FSR
Input-Referred Noise 75 µVRMS
DYNAMIC SPECIFICATIONS (Note 6)
Maximum Sampling Rate fSAMPLE fSAMPLE = fCLK / 2 1.024 Msps
Conversion Time (Pipeline 4 fSAMPLE
Delay/Latency) Cycles
Acquisition Time tACQ To full-scale step (0.006%) 100 ns
Overvoltage Recovery Time tOVR 410 ns
Aperture Delay tAD 3 ns
Full-Power Bandwidth 3.3 MHz
Small-Signal Bandwidth 78 MHz
2 _______________________________________________________________________________________
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
ELECTRICAL CHARACTERISTICS (continued) MAX1205
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz,
digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 99.5kHz 78 83
Signal-to-Noise Ratio SNR fIN = 300.5kHz 81.5 dB
(Note 5)
fIN = 504.5kHz 80
fIN = 99.5kHz 84 91
Spurious-Free Dynamic Range SFDR fIN = 300.5kHz 88 dB
(Note 5)
fIN = 504.5kHz 87
fIN = 99.5kHz -86 -80
Total Harmonic Distortion THD fIN = 300.5kHz -85 dB
(Note 5)
fIN = 504.5kHz -84
fIN = 99.5kHz 77 82
Signal-to-Noise Ratio plus SINAD fIN = 300.5kHz 79 dB
Distortion (Note 5)
fIN = 504.5kHz 78
POWER REQUIREMENTS
Analog Supply Voltage AVDD 4.75 5 5.25 V
Analog Supply Current I(AVDD) 51 70 mA
Digital Supply Voltage DVDD 3 5.25 V
Digital Supply Current I(DVDD) 0.4 1.2 mA
Output Drive Supply Voltage DRVDD 3 DVDD V
Output Drive Supply Current I(DRVDD) 10pF loads on D0–D13 and DAV 0.1 0.6 mA
Power Dissipation PDSS 257 377 mW
Warm-Up Time 0.1 sec
Power-Supply Rejection Ratio PSRR Offset 55 dB
Gain 55
_______________________________________________________________________________________ 3
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
MAX1205 TIMING CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Conversion Time tCONV 4 / fSAMPLE ns
Clock Period tCLK 488 ns
Clock High Time tCH 187 244 301 ns
Clock Low Time tCL 187 244 301 ns
Acquisition Time tACQ tCLK / 2 ns
Output Delay tOD 70 150 ns
DAV Pulse Width tDAV 1 / fCLK ns
CLK-to-DAV Rising Edge tS 65 145 ns
Data Access Time tAC CL = 20pF 16 75 ns
Bus Relinquish Time tREL 16 75 ns
Calibration Time tCAL ST_CAL = 1, Figure 8 17,400 fCLK
cycles
DIGITAL INPUTS AND OUTPUTS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage VIL 0.8 V
Input High Voltage VIH DVDD V
- 0.8
Input Capacitance 4 pF
CLK Input Low Voltage CLKVIL 0.8 V
CLK Input High Voltage CLKVIH AVDD V
- 0.8
CLK Input Capacitance CCLK 9 pF
Digital Input Current IIN_ VIN_ = 0 or DVDD ±0.1 ±10 µA
Clock Input Current ICLK -10 ±1 +10 µA
Output Low Voltage VOL ISINK = 1.6mA 70 400 mV
Output High Voltage VOH ISOURCE = 200µA DVDD DVDD V
- 0.4 - 0.03
Three-State Leakage Current ILEAKAGE ±0.1 ±10 µA
Three-State Output Capacitance COUT 3.5 pF
Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2: For unipolar mode, the analog input voltage VINP must be within 0V and VREF, VINN = VREF / 2; where VREF = VRFPS - VRFNS.
For differential mode, the analog inputs INP and INN must be within 0V and VREF; where VREF = VRFPS - VRFNS. The com-
mon mode of the inputs INP and INN is VREF / 2.
Note 3: Minimum and maximum parameters are not tested. Guaranteed by design.
Note 4: RI varies inversely with sample rate.
Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%.
Note 6: All AC specifications are shown for the differential mode.
4 _______________________________________________________________________________________
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
Typical Operating Characteristics MAX1205
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz,
calibrated, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIFFERENTIAL NONLINEARITY vs. SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE
TWO’S COMPLEMENT OUTPUT CODE TWO’S COMPLEMENT OUTPUT CODE vs. INPUT AMPLITUDE (fIN = 99.5kHz)
1.25 MAX1205-01 1.0 MAX1205-02 120 MAX1205-03
1.00 110 dBFS
0.75 0.5 100
0.50 90
INL (LSB) 0.25 DNL (LSB) SFDR (dB)
0 0 80
-0.25 70
-0.50 60
-0.5 dBc
-0.75 50
-1.00 40
-1.25 -1.0 30
-8192 -6144 -4096 -2048 0 2048 4096 6144 8192 -8192 -6144 -4096 -2048 0 2048 4096 6144 8192 -80 -70 -60 -50 -40 -30 -20 -10 0
TWO’S COMPLEMENT OUTPUT CODE TWO’S COMPLEMENT OUTPUT CODE INPUT AMPLITUDE (dBFS)
SIGNAL-TO-NOISE RATIO PLUS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIO
DISTORTION vs. INPUT FREQUENCY vs. INPUT FREQUENCY vs. INPUT FREQUENCY
84 MAX1205-04 MAX1205-05 85 MAX1205-06
82 AIN = -0.5dBFS -76
AIN = -20dBFS AIN = -0.5dBFS
80 -78 80
78 AIN = -6dBFS -80 AIN = -6dBFS AIN = -6dBFS
SINAD (dB) 76 THD (dB) SNR (dB) 75
74 -82
72 -84 70
70 -86
68 65
66 -88 AIN = -0.5dBFS AIN = -20dBFS
AIN = -20dBFS
64 -90 60
1 10 100 1000 1 10 100 1000 1 10 100 1000
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION TYPICAL FFT
vs. SAMPLING RATE (fIN = 99.5kHz) (fIN = 99.5kHz, 2048 VALUE RECORD)
85 MAX1205-07 MAX1205-08
AIN = -0.5dBFS -15
84 -30
AMPLITUDE (dBFS) -45
SINAD (dB) 83 -60
-75
82 -90
-105
81 -120
-135
80 0
0.1 1 0 100 200 300 400 500 600
SAMPLE RATE (Msps) FREQUENCY (kHz)
_______________________________________________________________________________________ 5
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
MAX1205 Typical Operating Characteristics (continued)
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz,
calibrated, TA = +25°C, unless otherwise noted.)
TYPICAL FFT EFFECTIVE NUMBER OF BITS
(fIN = 504.5kHz, 2048 VALUE RECORD) vs. INPUT FREQUENCY
MAX1205-09 14.0 MAX1205-10
-15 13.5 AIN = -0.5dBFS
-30
-45 13.0
AMPLITUDE (dBFS) -60 ENOB (Bits) 12.5 AIN = -6dBFS
-75 12.0
-90 11.5
-105
-120 11.0
-135 10.5 AIN = -20dBFS
0 10.0
0 100 200 300 400 500 600 1 10 100 1000
FREQUENCY (kHz) INPUT FREQUENCY (kHz)
Pin Description
PIN NAME FUNCTION
Digital Input to Start Calibration.
1 ST_CAL ST_CAL = 0: Normal conversion mode.
ST_CAL = 1: Start self-calibration.
2, 4, 5 AGND Analog Ground
3, 6 AVDD Analog Power Supply, +5V ±5%
7 DOR Data Out-of-Range Bit
8 D13 Bit 13 (MSB)
9 D12 Bit 12
10 D11 Bit 11
11 D10 Bit 10
12 D9 Bit 9
13 D8 Bit 8
14 D7 Bit 7
15 D6 Bit 6
16 DRVDD Digital Power Supply for the Output Drivers, +3V to +5.25V, DRVDD ≤ DVDD
17, 28, 29 DGND Digital Ground
18 D5 Bit 5
19 D4 Bit 4
20 D3 Bit 3
21 D2 Bit 2
22 D1 Bit 1
23 D0 Bit 0 (LSB)
24 TEST3 Test Pin 3. Leave unconnected.
6 _______________________________________________________________________________________
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
Pin Description (continued) MAX1205
PIN NAME FUNCTION
25 TEST2 Test Pin 2. Leave unconnected.
26 TEST1 Test Pin 1. Leave unconnected.
27, 30 DVDD Digital Power Supply, +3V to +5.25V
31 CLK Input Clock. Receives power from AVDD to reduce jitter.
32 DAV Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other
data-acquisition system.
Output Enable Input.
33 OE OE = 0: D0-D13 and DOR are high impedance.
OE = 1: All bits are active.
34 TEST0 Test Pin 0. Leave unconnected.
35 CM Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages.
36 RFPF Positive Reference Voltage. Force input.
37 RFPS Positive Reference Voltage. Sense input.
38 RFNF Negative Reference Voltage. Force input.
39 RFNS Negative Reference Voltage. Sense input.
40 INP Positive Input Voltage
41, 42 N.C. Not Connected. No internal connection.
43 INN Negative Input Voltage
Digital Output for End of Calibration.
44 END_CAL END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.
_______________Detailed Description passed on to the next stage. The accuracy of the con-
verter is improved by a digital calibration algorithm
Converter Operation which corrects for mismatches between the capacitors
The MAX1205 is a 14-bit, monolithic, analog-to-digital in the switched capacitor MDAC. Note that the pipeline
converter (ADC) capable of conversion rates up to introduces latency of four sampling periods between
1Msps. It uses a multistage, fully differential pipelined the input being sampled and the output appearing at
architecture with digital error correction and self-cali- D13–D0.
bration to provide typically greater than 91dB spurious- While the device can handle both single-ended and dif-
free dynamic range at a 1Msps sampling rate. Its ferential inputs (see Requirements for Reference and
signal-to-noise ratio, harmonic distortion, and intermod- Analog Signal Inputs), the latter mode of operation will
ulation products are also consistent with 14-bit accura- guarantee best THD and SFDR performance. The dif-
cy up to the Nyquist frequency. This makes the device ferential input provides the following advantages com-
suitable for applications such as imaging, scanners, pared to a single-ended operation:
data acquisition, and digital communications. • Twice as much signal input span
Figure 1 shows the simplified, internal structure of the • Common-mode noise immunity
ADC. A switched-capacitor pipelined architecture is
used to digitize the signal at a high throughput rate. • Virtual elimination of the even-order harmonics
The first four stages of the pipeline use a low-resolution • Less stringent requirements on the input signal
quantizer to approximate the input signal. The multiply- processing amplifiers
ing digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
_______________________________________________________________________________________ 7
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
MAX1205 RFP_ RFN_ CM AVDD AGND
STAGE1 STAGE2 STAGE3 STAGE4
INP S/H 8X ADC
INN
ADC MDAC
7
CLK CLOCK DAV
DVDD GENERATOR CORRECTION AND
CALIBRATION LOGIC END_CAL
ST_CAL
DGND 17
OE MAX1205
OUTPUT DRIVERS
DRVDD
DOR D13–D0
Figure 1. Internal Block Diagram
Requirements for Reference resistance on chip. They also drive a switched capaci-
and Analog Signal Inputs tor of 21pF. To meet the dynamic performance, the ref-
Fully differential switched-capacitor circuits (SC) are erence voltage is required to settle to 0.0015% within
used for both the reference and analog inputs (Figure 2). one clock cycle. Accomplish this by choosing an
This allows either single-ended or differential signals to appropriate driving circuit (Figure 4). The capacitors at
be used in the reference and/or analog signal paths. the reference pins (RFPF, RFNF) provide the dynamic
The signal voltage on these pins (INP, INN, RFN_, charge required during each clock cycle, while the op
RFP_) should never exceed the analog supply rail, amps ensure accuracy of the reference signals. These
AVDD, and should not fall below ground. capacitors must have low dielectric-absorption charac-
Choice of Reference teristics, such as polystyrene or teflon capacitors.
It is important to choose a low-noise reference, such as The reference pins can be connected to either single-
the MAX6341, which can provide both excellent load ended or differential voltages within the specified maxi-
regulation and low temperature drift. The equivalent mum levels. Typically the positive reference pin (RFPF)
input circuit for the reference pins is shown in Figure 3. would be driven to 4.096V, and the negative reference
Note that the reference pins drive approximately 1kΩ of pin (RFNF) connected to analog ground. There are
sense pins, RFPS and RFNS, which can be used with
CM RFPS
RFPF
RFPF
INP
RFNF
INN
RFPF RFNF
CM RFNS
Figure 2. Simplified MDAC Architecture Figure 3. Equivalent Input at the Reference Pins. The sense
pins should not draw any DC current.
8 _______________________________________________________________________________________
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
external amplifiers to compensate for any resistive drop gle-ended inputs. In this case, convert the single- MAX1205
on these lines, internal or external to the chip. Ensure a ended signals into differential ones by using the circuit
correct reference voltage by using proper Kelvin con- recommended in Figure 5. Use low-noise, wideband
nections at the sense pins. amplifiers such as the MAX4108 to maintain the signal
Common-Mode Voltage purity over the full-power bandwidth of the MAX1205
The switched capacitor input circuit at the analog input input.
allows signals between AGND and the analog power Lowpass or bandpass signals may be required to
supply. Since the common-mode voltage has a strong improve the signal-to-noise-and-distortion ratio of the
influence on the performance of the ADC, the best incoming signal. For low-frequency signals (