1 //Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.2 //--------------------------------------------------------------------------------3 //Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 20174 //Date : Sun Mar 22 12:40:33 20205 //Host : DESKTOP-CE32R3P running 64-bit major release (build 9200)6 //Command : generate_target video_system_wrapper.bd7 //Design : video_system_wrapper8 //Purpose : IP block netlist9 //--------------------------------------------------------------------------------
10 `timescale 1 ps / 1ps11
12 modulevideo_system_wrapper13 (aclk_0,14 aresetn_0,15 camera_rstn,16 din_0,17 en_capture_0,18 href_0,19 locked_0,20 m_axis_video_0_tdata,21 m_axis_video_0_tlast,22 m_axis_video_0_tready,23 m_axis_video_0_tuser,24 m_axis_video_0_tvalid,25 overflow_0,26 pclk_0,27 s_axis_video_0_tdata,28 s_axis_video_0_tlast,29 s_axis_video_0_tready,30 s_axis_video_0_tuser,31 s_axis_video_0_tvalid,32 status_0,33 underflow_0,34 vga_clk,35 vid_io_out_0_active_video,36 vid_io_out_0_data,37 vid_io_out_0_field,38 vid_io_out_0_hblank,39 vid_io_out_0_hsync,40 vid_io_out_0_vblank,41 vid_io_out_0_vsync,42 vid_io_out_reset_0,43 vsync_0,44 vtc_ctrl_araddr,45 vtc_ctrl_arready,46 vtc_ctrl_arvalid,47 vtc_ctrl_awaddr,48 vtc_ctrl_awready,49 vtc_ctrl_awvalid,50 vtc_ctrl_bready,51 vtc_ctrl_bresp,52 vtc_ctrl_bvalid,53 vtc_ctrl_rdata,54 vtc_ctrl_rready,55 vtc_ctrl_rresp,56 vtc_ctrl_rvalid,57 vtc_ctrl_wdata,58 vtc_ctrl_wready,59 vtc_ctrl_wstrb,60 vtc_ctrl_wvalid);61 inputaclk_0;62 inputaresetn_0;63 outputcamera_rstn;64 input [7:0]din_0;65 inputen_capture_0;66 inputhref_0;67 outputlocked_0;68 output [23:0]m_axis_video_0_tdata;69 outputm_axis_video_0_tlast;70 inputm_axis_video_0_tready;71 outputm_axis_video_0_tuser;72 outputm_axis_video_0_tvalid;73 outputoverflow_0;74 inputpclk_0;75 input [23:0]s_axis_video_0_tdata;76 inputs_axis_video_0_tlast;77 outputs_axis_video_0_tready;78 inputs_axis_video_0_tuser;79 inputs_axis_video_0_tvalid;80 output [31:0]status_0;81 outputunderflow_0;82 inputvga_clk;83 outputvid_io_out_0_active_video;84 output [23:0]vid_io_out_0_data;85 outputvid_io_out_0_field;86 outputvid_io_out_0_hblank;87 outputvid_io_out_0_hsync;88 outputvid_io_out_0_vblank;89 outputvid_io_out_0_vsync;90 inputvid_io_out_reset_0;91 inputvsync_0;92 input [8:0]vtc_ctrl_araddr;93 outputvtc_ctrl_arready;94 inputvtc_ctrl_arvalid;95 input [8:0]vtc_ctrl_awaddr;96 outputvtc_ctrl_awready;97 inputvtc_ctrl_awvalid;98 inputvtc_ctrl_bready;99 output [1:0]vtc_ctrl_bresp;100 outputvtc_ctrl_bvalid;101 output [31:0]vtc_ctrl_rdata;102 inputvtc_ctrl_rready;103 output [1:0]vtc_ctrl_rresp;104 outputvtc_ctrl_rvalid;105 input [31:0]vtc_ctrl_wdata;106 outputvtc_ctrl_wready;107 input [3:0]vtc_ctrl_wstrb;108 inputvtc_ctrl_wvalid;109
110 wireaclk_0;111 wirearesetn_0;112 wirecamera_rstn;113 wire [7:0]din_0;114 wireen_capture_0;115 wirehref_0;116 wirelocked_0;117 wire [23:0]m_axis_video_0_tdata;118 wirem_axis_video_0_tlast;119 wirem_axis_video_0_tready;120 wirem_axis_video_0_tuser;121 wirem_axis_video_0_tvalid;122 wireoverflow_0;123 wirepclk_0;124 wire [23:0]s_axis_video_0_tdata;125 wires_axis_video_0_tlast;126 wires_axis_video_0_tready;127 wires_axis_video_0_tuser;128 wires_axis_video_0_tvalid;129 wire [31:0]status_0;130 wireunderflow_0;131 wirevga_clk;132 wirevid_io_out_0_active_video;133 wire [23:0]vid_io_out_0_data;134 wirevid_io_out_0_field;135 wirevid_io_out_0_hblank;136 wirevid_io_out_0_hsync;137 wirevid_io_out_0_vblank;138 wirevid_io_out_0_vsync;139 wirevid_io_out_reset_0;140 wirevsync_0;141 wire [8:0]vtc_ctrl_araddr;142 wirevtc_ctrl_arready;143 wirevtc_ctrl_arvalid;144 wire [8:0]vtc_ctrl_awaddr;145 wirevtc_ctrl_awready;146 wirevtc_ctrl_awvalid;147 wirevtc_ctrl_bready;148 wire [1:0]vtc_ctrl_bresp;149 wirevtc_ctrl_bvalid;150 wire [31:0]vtc_ctrl_rdata;151 wirevtc_ctrl_rready;152 wire [1:0]vtc_ctrl_rresp;153 wirevtc_ctrl_rvalid;154 wire [31:0]vtc_ctrl_wdata;155 wirevtc_ctrl_wready;156 wire [3:0]vtc_ctrl_wstrb;157 wirevtc_ctrl_wvalid;158
159 video_system video_system_i160 (.aclk_0(aclk_0),161 .aresetn_0(aresetn_0),162 .camera_rstn(camera_rstn),163 .din_0(din_0),164 .en_capture_0(en_capture_0),165 .href_0(href_0),166 .locked_0(locked_0),167 .m_axis_video_0_tdata(m_axis_video_0_tdata),168 .m_axis_video_0_tlast(m_axis_video_0_tlast),169 .m_axis_video_0_tready(m_axis_video_0_tready),170 .m_axis_video_0_tuser(m_axis_video_0_tuser),171 .m_axis_video_0_tvalid(m_axis_video_0_tvalid),172 .overflow_0(overflow_0),173 .pclk_0(pclk_0),174 .s_axis_video_0_tdata(s_axis_video_0_tdata),175 .s_axis_video_0_tlast(s_axis_video_0_tlast),176 .s_axis_video_0_tready(s_axis_video_0_tready),177 .s_axis_video_0_tuser(s_axis_video_0_tuser),178 .s_axis_video_0_tvalid(s_axis_video_0_tvalid),179 .status_0(status_0),180 .underflow_0(underflow_0),181 .vga_clk(vga_clk),182 .vid_io_out_0_active_video(vid_io_out_0_active_video),183 .vid_io_out_0_data(vid_io_out_0_data),184 .vid_io_out_0_field(vid_io_out_0_field),185 .vid_io_out_0_hblank(vid_io_out_0_hblank),186 .vid_io_out_0_hsync(vid_io_out_0_hsync),187 .vid_io_out_0_vblank(vid_io_out_0_vblank),188 .vid_io_out_0_vsync(vid_io_out_0_vsync),189 .vid_io_out_reset_0(vid_io_out_reset_0),190 .vsync_0(vsync_0),191 .vtc_ctrl_araddr(vtc_ctrl_araddr),192 .vtc_ctrl_arready(vtc_ctrl_arready),193 .vtc_ctrl_arvalid(vtc_ctrl_arvalid),194 .vtc_ctrl_awaddr(vtc_ctrl_awaddr),195 .vtc_ctrl_awready(vtc_ctrl_awready),196 .vtc_ctrl_awvalid(vtc_ctrl_awvalid),197 .vtc_ctrl_bready(vtc_ctrl_bready),198 .vtc_ctrl_bresp(vtc_ctrl_bresp),199 .vtc_ctrl_bvalid(vtc_ctrl_bvalid),200 .vtc_ctrl_rdata(vtc_ctrl_rdata),201 .vtc_ctrl_rready(vtc_ctrl_rready),202 .vtc_ctrl_rresp(vtc_ctrl_rresp),203 .vtc_ctrl_rvalid(vtc_ctrl_rvalid),204 .vtc_ctrl_wdata(vtc_ctrl_wdata),205 .vtc_ctrl_wready(vtc_ctrl_wready),206 .vtc_ctrl_wstrb(vtc_ctrl_wstrb),207 .vtc_ctrl_wvalid(vtc_ctrl_wvalid));208 endmodule
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