FPGA TIMING CONSTRIANT(.sdc)

目录

WHY WE NEED TIMING CONSTRAINT:

Part 1（set "false" path inside FPGA）

1.set_multicycle_path

          2.set_max_delay/set_min_delay

3.set_false_path

4.set_clock_group

         PART 2(I/O delay)

         PART 3 (SOME TIPS WITH TIMING CONSTRAINTS)

REFERENCE

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WHY WE NEED TIMING CONSTRAINT:

RELAX TIMING REQUIREMENTS

Nomally set on "not real critical path"

Some logic paths need more than 1 cycle to propogate to next squential cell

Diffrenet delays in FPGA

Definition of slack

• setup time: the amount of time the data at the synchronous input (D) must be stable before the active edge of clock
• hold time:   the amount of time the data at the synchronous input (D) must be stable after the active edge of clock
•  (Arrival time) < (MAX_DELAY – Tsetup), (Arrival time) > (MIN_DELAY +Thold)

Part 1（set "false" path inside FPGA）

1.set_multicycle_path

effect both setup/hold times, this is kinda like adding "pipeline" to the path. like 

If you want the same delay for both setup time and hold time, for example N cycle, uses

set_multicycle_path -from [get_pins  UFF0/Q] -to  [get_pins UFF1/D]-setup 4 //delay 4 clock cyc
set_multicycle_path -from [get_pins  UFF0/Q] -to [get_pins UFF1/D] -hold 3  // delay 3 clock cyc

Reference:

Setting Multicycle Path Exceptions

set_max_skew(qaurtus only)

set_max_skew -from_clock { clock } -to_clock { * } -from foo -to blat 2

Use the set_max_skew constraint to perform maximum
allowable skew analysis between sets of registers or
ports. In order to constrain skew across multiple
paths,