[ARM-assembly]-A64指令集合总结

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1、Instructions that move System or Special-purpose registers to or from a general-purpose register

MRS MSR

2、Floating-point moves between a SIMD&FP register and a general-purpose register

• FMOV (between a general-purpose register and a half-precision register).
• FMOV (between a general-purpose register and a single-precision register).
• FMOV (between a general-purpose register and a double-precision register).
• FMOV (between a general-purpose register and a SIMD element).

3、SIMD moves between a SIMD&FP register and a general-purpose register

• INS (from a general-purpose register to a SIMD element).
• UMOV (from a SIMD element to a general-purpose register).

4、Barriers

• DMB.
• DSB.
• ESB, when the RAS Extension is implemented.
• ISB.
• PSB, when the Statistical Profiling Extension is implemented.
• SB, when ARMv8.0-SB is implemented.

5、Memory access instructions at various access sizes

• LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW (immediate, not literal).
• LDUR, LDURB, LDURH, LDURSB, LDURSH, LDURSW (immediate).
• LDTR, LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW (immediate).
• LDAR, LDARB, LDARH, LDXR, LDXRB, LDXRH, LDAXR, LDAXRB, LDAXRH.
• LDXP, LDAXP.
• STR, STRB, STRH (immediate)
• STUR, STURB, STURH (immediate).
• STTR,STTRB, STTRH (immediate).
• STLR, STLRB, STLRH, STXR, STXRB, STXRH, STLXR, STLXRB, STLXRH.
• STXP, STLXP.
• LDLAR, LDLARB, LDLARH - Armv8.1 instructions.
• STLLR, STLLRBB, STLLRH - Armv8.1 instructions.
• CAS, CASB, CASH, CASP - Armv8.1 instructions.
• SWP, SWPB, SWPH - Armv8.1 instructions.
• LDADD, LDADDB, LDADDH - Armv8.1 instructions.
• LDCLR, LDCLB, LDCLRH - Armv8.1 instructions.
• LDEOR, LDEORB, LDEORH - Armv8.1 instructions.
• LDSET, LDSETB, LDSETH - Armv8.1 instructions.
• LDSMAX, LDSMAXB, LDSMAXH - Armv8.1 instructions.
• LDSMIN, LDSMINB, LDSMINH - Armv8.1 instructions.
• LDUMAX, LDUMAXB, LDUMAXH - Armv8.1 instructions.
• LDUMIN, LDUMINB, LDUMINH - Armv8.1 instructions.
• STADD, STADDB, STADDH - Armv8.1 instructions.
• STCLR, STCLB, STCLRH - Armv8.1 instructions.
• STEOR, STEORB, STEORH - Armv8.1 instructions.
• STSET, STSETB, STSETH - Armv8.1 instructions.
• STSMAX, STSMAXB, STSMAXH - Armv8.1 instructions.
• STSMIN, STSMINB, STSMINH - Armv8.1 instructions.
• STUMAX, STUMAXB, STUMAXH - Armv8.1 instructions.
• STUMIN, STUMINB, STUMINH - Armv8.1 instructions.
• LDAPR, LDAPRB, LDAPRH - Armv8.3 instructions.
• LDAPURH, LDAPURSH, LDAPUR, LDAPURSW, LDAPURSB, LDAPURB - Armv8.4 instructions.
• STLUR, STLURH, STLURB - Armv8.4 instructions.

6、Move immediate to general-purpose register

• MOVZ, MOVN, MOVK (immediate).
• MOV (between a general-purpose register and the stack pointer)

7、System instructions, Send Event, NOP, and Clear Exclusive

• IC.
• DC.
• TLBI.
• AT.
• SEV, SEVL.
• NOP.
• CLREX.

8、Memory Tagging Extension Instructions(ARMv8.5-MemTag)

• ADDG <Xd|SP>, <Xn|SP>, #, #
• SUBG <Xd|SP>, <Xn|SP>, #, #
• STG , [<Xn|SP>{, #}], signed offset.
• STZG , [<Xn|SP>{, #}], signed offset.
• ST2G , [<Xn|SP>{, #}], signed offset.
• STZ2G , [<Xn|SP>{, #}], signed offset.
• LDG , [<Xn|SP>{, #}]
• LDGM , [<Xn|SP>]
• STGM , [<Xn|SP>]
• STZGM , [<Xn|SP>]
• STGP , , [<Xn|SP>{, #}]

9、Exception-generating instructions

• SVC.
• HVC.
• SMC.
• BRK.
• HLT.

10、Instructions that explicitly write to the PC (branches)

B, B.cond, BL, BLR, BR, CBZ, CBNZ, RET, TBZ, TBNZ

11、Exception return and related instructions

• ERET.

12、Instructions that request entry to a low-power state

• WFE, WFI.

13、Instructions that read the PC

• LDR (literal), LDRSW (literal).
• ADR, ADRP.
• PRFM (literal).

14、Instructions that explicitly modify PSTATE, other than DCPS and DRPS

• ADDS, SUBS, ADCS, SBCS, ANDS, BICS, CCMN, CCMP.
• FCMP, FCMPE, FCCMP, FCCMPE.
• MSR DAIFSet (immediate), MSR DAIFClr (immediate), MSR SPSel (immediate).
• MSR NZCV (register), MSR DAIF (register), MSR SPSel (register).

15、Instructions that read PSTATE.{N, Z, C, V} or other PSTATE fields

• CSEL, CSINC, CSINV, CSNEG, CCMN, CCMP, FCSEL, FCCMP, FCCMPE.
• ADC, ADCS,SBC, SBCS.
• CFINV.
• MRS NZCV, MRS DAIF, MRS SPSel, MRS CurrentEL.

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