Y86 Instruction set Architecture
【Better Explained】
Y86 Programs
Some Y86 Instruction Details
push %esp
pop %esp
Processor's State
Program Registers
Condition Codes
Program Counter (PC)
Memory
Program States
AOK
HLT
ADR
INS
Instruction set
Four movl instructions
Four integer operation instructions
The seven jump instructions
Six conditional move instructions
The call instruction pushes the return address on the stack and jumps to the destination address.
The ret instruction returns from such a call.
The pushl and popl instructions
The halt instruction
Instruction Encoding
【Better Explained】
Initial byte
the higher 4 bits , code part
the lower 4 bits ,function part
register specifier byte
4-byte constant word
Exceptions
Sequential Y86 Implementations
Organizing Processing into Stages
Fetch
取指
Decode
译码
Execute
执行
Memory
访存
Write back
写回
PC update
SEQ Hardware Structure
Fetch
Hardware Unit
Instruction memory
PC incrementer
Control logic blocks
Program stat
Decode
Hardware Unit
Register file
A
B
Control logic blocks
srcA
srcB
Program stat
Execute
Hardware Unit
ALU
CC
Control logic blocks
ALU B
ALU fun
ALU A
Program stat
Memory
Hardware Unit
Virtual Memory System
Control logic blocks
Mem. control
Addr
Data
Program stat
Write back
Hardware Unit
Register file
E
M
Control logic blocks
dstM
dstE
Program stat
PC update
SEQ Timing
【Better Explained】
The processor never needs to read back the state updated by an instruction in order to complete the processing of this instruction.
Some rule in Y86
PC is loaded with a new instruction address every clock cycle
CC is loaded only when an integer operation instruction is executed.
Virtual memory is written only when an rmmovl pushl or call instruction is executed.
Hardware unit that require Clock Sequence control
Clocked registers
PC
CC
Random-access memories
Virtual memory system
The register file
SEQ stage implementations
Fetch Stage
seq_fetch.png
Decode & Write back
seq_decode&writeback.png
Execute Stage
seq_execute.png
Memory Stage
seq_memory.png
PC update Stage
seq_PC.png
Pipelined Y86 Implementations
SEQ+: Rearranging the Computation Stages
Circuit Retiming
Inserting Pipeline Registers
Rearranging and Relabeling Signals
Next PC Prediction
Branch Prediction
Pipeline Hazards
Data Hazard
Program registers
Control Hazard
PC
Mispredicted branches
Ret instructions require special handing
Avoiding Data Hazards by Stalling
Avoiding Data Hazards by Forwarding
Data forwarding
Bypassing
Load/Use Data Hazards
One class of data hazards cannot be handled purely by forwarding,because memory reads occur late in the pipeline. 言外之意,就是内存中的值 valM 不像 valE 从一开始出现就是被钉死了的。本质原因还是出来的晚,CSAPP言简意赅。
Load inerlock
Exception Handling
Inner Exception
Halt
illegal Instruction that combine code and fun
Fetch,read or write a illegal address
Excepting instruction
Exception Handler
This is the one for your OS
Some details
The higher priority,the deeper of a instruction,that will be reported to your OS
A excepting instruction occurs after a mispredicted branch
The different stage in pipeline will be updated by different instruction. For instance ,if there is some error in one stage of pipeline made by a malicious instruction will effect other instruction that should not be executed.
Some mechanism
Take stat and other information to Program stat and W_register
PIPE Stage Implementations
PC Selection and Fetch Stage
Decode and Write-Back Stage
Execute Stage
Memory Stage
Pipeline Control Logic
Special logic control cases
Processing ret
The pipeline must stall until the ret instruction reaches the write-back stage.
Load/use hazard
The pipeline must stall for one cycle between an instruction that reads a value from memory and an instruction that uses this value.
Mispredicted branches
By the time the branch logic detects that a jump should not have been taken,several instructions at the branch target will have started down the pipeline. These instructions must be removed from the pipeline.
Instruction squashing
Exception
【Better Explained】
Bad stuff
There are two stage will make exception:Fetch and Memory
There are three stage will update the new program stat:Execute Memory and Write-back
If an instruction leads an exception ,we forbid the later instruction updating the programmer-visible stat. In addition , when the excepting instruction reaches the write-back stage,we stop the application.
Detecting Special Control Conditions
Pipeline Control Mechanisms
Combinations of Control Conditions
Control logic implementation