Altium Designer 约束规则设计

DR整体呈树状。
DR由first object，second object，constraint构成。
当DRC运行时，
first ，是第一个pick的对象，例如track，pad等，
second，是第二个pick的对象，例如track，pad等。
constraints是一个matrix，row是first，column是second，交叉处，就是constraint value，
由于first和second，是互易的，所以matrix是只有斜向一半的。

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rule priority，
object会按照优先级检查violation，
当object能适用多个DR时，会进行仲裁，将high priority的DR套用给object，
如果object按照high priority检查后，是passed状态，没有violation,那么跳出。
如果object按照high priority检查后，是violation状态，则上报violation。

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pad via template
在pcb panel中，
pad via template->all->local ，
找到顺眼的pad和 via，多选，
然后点击save as library，可以另存为一个pvlib。

之后，可以加载pvlib，
并在pcb pad via template 这个panel中，选择并使用。

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classes，
命令design->classes，可以打开object classed exploror，
在其中定义各种class。

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xSignals，
命令design->xsignals->create xsignals，可以打开create xsignal between component。
在其中定义xsignals。

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Room Definition

Room的运行机制，
第一类object，component，
first match中，
可以选择all，等同于命令InComponentClass(‘All Component’)，
选择Component，等同于命令InComponent(‘XXX’)，
选择ComponentClass，等同于命令InComponentClass(‘xxx’)，
选择custom query，是最灵活的方式。
这个环节，针对的是component，

然后就会对match的object，根据约束做进一步的判断，
有两种约束，
keep object inside，
对于match成功的component，
如果不在region内，则上报violation。

keep object outside，
对于match成功的component，
如果在region内，则上报violation。

当使用move room命令时，根据约束做进一步的处理。
如果是keep object inside，那么这些object会同步移动。
第一类object，component，
第二类object，track in region，via in region，
如果track的两个end，全在region内，就判定为match，否则为not match，
如果via的pad，全在region内，就判定为match，否则为not match，

对于match成功的component，track，via，会跟room同步，
当使用move room命令时，这些object会同步移动。

如果是keep object outside，
对于match成功的component，track，via，不会跟room同步，
当使用move room命令时，这些object不会同步移动。

在AD中，Room只能在placement->room definition中定义，
Toplayer，或bottomlayer，定义的是Room所在的位置。

通常使用keep object outside（或者keep object inside）和custom query= False的组合，来表示一个布线约束region。
首先判断object是否在region内，然后再判断query是否为true，如果为true，则报violation，
由于任何object的query值都强制为false，不会为true，所以任何object，都不会报violation，

当room不是用于布局，而是用于布线时，即调用withinroom函数时，
room不再与layer挂钩，而只与四角坐标挂钩，所以，此时room是一个柱状空间，而不是平面空间。

设置room时，使用命令
design->room->place rectangle room，
建议设置在板外，调整好尺寸后，使用命令
move selection，移动room到合适的位置。

移动整个room中的所有object，使用命令
desing->room->move room，

找到room的方法，
view config-> view option-> object visibility，
关闭all object，只打开rooms,和 pad
整板就只有room显示出来，方便操作。pad用于对位，
filter只选择room。

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常用custom query函数。

WithinRoom(‘BGA1’)，用于比对object的坐标，是否位于region的四角坐标之内，如果是，则返回true。

InPolygon，用于判断object是否是polygonpour的一部分，如果是，则返回true。

InLayerClass(‘xxx’)，用于判断object是否在layerclass之内，如果是，返回true。

OnLayer(‘xxx’)，用于判断object是否在layer之上，如果是，返回true。

InNetClass(‘xxx’)，用于判断object是否属于netclass，如果是，返回true。

InNet(‘xxx’)，用于判断object是否属于net，如果是，返回true。

InComponent(‘xxx’)，用于判断object是否属于component，如果是，返回true。

IsPad,用于判断object是否是pad，如果是，返回true。

IsVia,用于判断object是否是via，如果是，返回true。

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electrical
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clearance
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最基本的规则，
all to all规则，name就是clearance，其他的特定规则，则加后缀。例如clearanc_BGA1。
定义的是track和pad之间的minimum gap，一般设置为5mil，

polygon规则，
name是clearance_Polygon，
first match ，是custom query = InPolygon，
second match，是all,
value是 12mil。

keepout规则，
name是clearance_Keepout，
first match ，是custom query = InLayerClass(‘xxx’)，
second match，是custom query = OnLayer(‘xxx’)，,
value是 20mil。

BGA规则，
name是clearance_BGA，
first match ，是custom query = WithinRoom(‘BGA_1’) OR WithinRoom(‘BGA_2’) ，
second match，是all,
value是 4mil。

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shortcircuit
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只有一个all to all，
allow short = not choose，

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unroute
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只有一个all to all，
check for imcomplete = not choose，

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modified polygon
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只有一个all to all，
allow shelve = not choose，
allow modified = not choose，

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routing
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width
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最基本的规则，
all to all规则，name就是clearance，其他的特定规则，则加后缀。例如width_BGA1。
定义的是track的width，一般设置为8mil-8mil-20mil，

pwr规则，
name是width_pwr，
first match ，是custom query = InNet(‘xxx1’) or InNet(‘xxx2’)，
value是 12mil-20mil-40mil。

keepout规则，
name是clearance_Keepout，
first match ，是custom query = InLayerClass(‘xxx’)，
second match，是custom query = OnLayer(‘xxx’)，,
value是 20mil。

BGA规则，
name是width_BGA，
first match ，是custom query = WithinRoom(‘BGA_1’) OR WithinRoom(‘BGA_2’) ，
value是 4mil-5mil-12mil。

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routingtopology
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默认
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routingpriority
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默认
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routinglayer
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默认全选
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routingcorner
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默认

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routing via style
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routingvias规则，
first match是all，
hole value = 8mil-12mil-16mil，
pad value = 16mil-24mil-30mil，

routingvias_BGA规则，
first match是custom query = WithInRoom(‘BGA1’)，
hole value = 8mil-8mil-8mil，
pad value = 16mil-16mil-16mil，

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fanout control
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默认

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diff pair routing
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diffpairsrouting规则，
first match 是all，
max uncoupled length = 500mil，
min width = 5mil，
min gap = 5mil，
preferred width = 5mil，
preferred gap = 6mil，
max width = 16mil，
max gap = 16mil,

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SMT
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默认
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Mask
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solder mask expansion
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默认规则，
value = 4mil，
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paste mask expansion
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默认规则，
value = 0mil，

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plane
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power plane connect style
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默认规则，
value = direct，
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power plane clearance
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默认规则，
value = 5mil，

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polygon connect style
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默认规则 polygonconnect，all to all,
style = relief，
air gap width = 10mil,
conductor width = 25mil,
rotation = 90deg,
conductor number = 4,

polygonconnect_via，
first match 是custom query = IsVia，
second match是all,
style = direct，

polygon connect_pwr，
first match 是custom query = InNet(‘xxx1’) OR InNet(‘xxx2’)…
second match是all,
style = relief，
air gap width = 10mil,
conductor width = 40mil,
rotation = 90deg,
conductor number = 4,

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plane
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默认

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manufacture
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hole size
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默认规则，
value = 1mil-99999mil，

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hole to hole clearance
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默认规则，
value = 5mil，

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minimum solder mask sliver
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默认规则，
value = 1.5mil，

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silk to solder clearance
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默认规则，
first match，是custom query = IsPad,
second match，是all，
check mode = clearance to expand copper，
value = 2mil,

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silk to solder clearance
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默认规则，all to all，
value = 2mil,

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net antennae
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默认规则，all to all，
value = 0mil,

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high speed
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默认

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placement
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room definition
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由design->room->place rectangle room定义。
由design->room->move room修改位置。

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component clearance
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默认规则，all to all，
min vertical value = 8mil，
min horizontal value = 4mil，

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height
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默认规则，all to all，
value = 0mil-500mil-1000mil，

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signal integrity
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默认

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