linux查看系统的cpu信息,linux系统下cpu信息的查看

fpu: Onboard (x87) Floating Point Unit

vme: Virtual Mode Extension

de: Debugging Extensions

pse: Page Size Extensions

tsc: Time Stamp Counter: supportforRDTSC and WRTSC instructions

msr: Model-Specific Registers

pae: Physical Address Extensions: ability to access 64GB of memory; only 4GB can be accessed at atimethough

mce: Machine Check Architecture

cx8: CMPXCHG8 instruction

apic: Onboard Advanced Programmable Interrupt Controller

sep: Sysenter/Sy***it Instructions; SYSENTER is used for jumps to kernel memory during system calls, and SY***IT is used forjumps: back to the user code

mtrr: Memory Type Range Registers

pge: Page Global Enable

mca: Machine Check Architecture

cmov: CMOV instruction

pat: Page Attribute Table

pse36:36-bit Page Size Extensions: allows to map 4MB pages into the first 64GB RAM, used with PSE.

pn: Processor Serial-Number; only available on Pentium 3clflush: CLFLUSH instruction

dtes: Debug Trace Store

acpi: ACPI via MSR

mmx: MultiMedia Extension

fxsr: FXSAVE and FXSTOR instructions

sse: Streaming SIMD Extensions. Single instruction multiple data. Lets youdo a bunch of the same operation on different pieces of input: ina single clock tick.

sse2: Streaming SIMD Extensions-2. More of the same.

selfsnoop: CPU self snoop

acc: Automatic Clock Control

IA64: IA-64processor Itanium.

ht: HyperThreading. Introduces an imaginary second processor that doesn‘t do much but lets you run threads in the same process a bit quicker.

nx: No Execute bit. Prevents arbitrary code running via buffer overflows.

pni: Prescott New Instructions aka. SSE3

vmx: Intel Vanderpool hardware virtualization technology

svm: AMD"Pacifica"hardware virtualization technology

lm:"Long Mode," whichmeans the chip supports the AMD64 instruction set

tm:"Thermal Monitor" Thermal throttling with IDLE instructions. Usually hardware controlled inresponse to CPU temperature.

tm2:"Thermal Monitor 2″ Decrease speed by reducing multipler and vcore.

est: "Enhanced SpeedStep"

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文档共60页。主要向初学者提供了Zynq开发的技术方向,针对不同应用给出了基本的参考文档;同时对Zynq双核AMP加载方式做了详细描述,对Zynq的fsbl启动流程做了简单介绍。章节如下: Zynq User Guide 1 介绍 4 2 快速上手指南 4 3 多核开发教程 4 3.1 AMP开发说明 6 3.1.1 快速生成amp工程 6 3.1.2 Generating Boot File 8 3.1.3 烧写程序 9 3.1.4 启动 10 3.1.5 调试 10 3.1.6 总结 11 3.2 SMP开发说明 11 4 ZC706启动代码分析 11 4.1 启动代码 12 4.2 FSBL流程(FOR AMP) 13 4.3 CPU0启动CPU1流程 14 5 程序在线烧写方案及流程 14 5.1 程序烧写需求 14 5.2 提出该需求的原因 14 5.3 程序烧写方案 14 5.3.1 BOOT.BIN组成 14 5.3.2 BOOT.BIN生成方法 15 5.4 FSBL.BIN和APP.BIN等的生成 15 5.5 制作*BIN及烧写的具体步骤 15 5.5.1 制作*bin流程 15 5.5.2 BOOT.bin制作过程 15 5.5.3 FSBL.bin和APP.bin等的生成过程 22 5.6 烧写BOOT.BIN步骤 26 5.6.1 通过SDK工具烧写步骤 26 5.6.2 通过上位机烧写软件的烧写步骤 29 5.6.3 通过串口调试助手烧写步骤 29 6 Zynq Qspi控制器 30 6.1 基本特性 30 6.2 I/O接口 31 6.3 QSPI控制器模式 33 6.3.1 I/O模式 33 6.3.2 线性地址(linear address)模式 33 6.3.3 传统(legacy)SPI模式 34 6.4 QSPI 例程 34 6.5 QSPI控制器支持访问32MB方法 35 6.5.1 Bank地址寄存器(Bank address register) 35 6.5.2 扩展地址模式(Extended address mode) 35 6.5.3 使用新写命令(New commands) 35 6.6 QSPI FLASH选择 35 6.7 作为BOOT器件考虑 35 7 µC/OS系统启动指南 36 7.1 INTRODUCTION 36 7.1.1 Software Requirements 36 7.1.2 Hardware Requirements 36 7.2 HARDWARE DESIGN 37 7.2.1 Step 1. Invoke the Vivado IDE and Create a project 37 7.2.2 Step 2. Create an IP Integrator Design 39 7.2.3 Step 3. Add and setup the Zynq processor system IP block 39 7.2.4 Step 4. Customize the Zynq block for our design 41 7.2.5 Step 5. Add the soft peripherals 45 7.2.6 Step 6. Generate HDL Design Files 47 7.2.7 Step 7. Synthesis, Implement and Generate Bitstream 48 7.3 SOFTWARE DESIGN 49 7.3.1 Step 1. Installation of the µC/OS Repository 49 7.3.2 Step 2. Generate the µC/OS BSP 50 7.3.3 Step 3. Build and Debug the Demonstration Project 54 7.3.4 Step 4. Program the AXI Timer 0 with the ucos_axitimer Driver 55 7.3.5 Step 5. Program the AXI Timer 1 with the Xilinx tmrctr Driver 58 7.4 CONCLUSION 59 8 Linux系统启动指南 59
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