html5for循环列表1980年,MAX1980 Datasheet(数据表) 5 Page - Maxim Integrated Products

Quick-PWM Slave Controller with

Driver Disable for Multiphase DC-DC Converter

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5

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= 5V, VOUT= VCOMP= 1.2V, VCM+= VCM-= VCS+= VCS-= 1.2V, DD = VCC, TA= -40°C

to +100°C, unless otherwise noted.) (Note 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CURRENT SENSING

On-Time Adjustment Range

0.42V < VCOMP< 2.8V, VOUT

≥ 0.7V

-40

+40

%

COMP Output Current

ICOMP

Sink and source

30

µA

Current-Balance Offset

(VCM+- VCM-) - (VCS+- VCS-), ICOMP= 0,

-100mV

≤ (VCM+- VCM-) ≤ +100mV

-2.0

+2.0

mV

Current-Sense, Common-Mode

Range

CM+, CM-, CS+, CS-

-0.2

+2.0

V

VILIM= 0.5V

47.5

52.5

Positive Current-Limit Threshold

VC_LIM

VCM+- VCM-and

VCS+- VCS-

VILIM= 1V

97

103

mV

VILIM= 0.5V

-80

-70

Negative Current-Limit

Threshold

VCS+- VCS-

VILIM= 1V

-160

-140

mV

ILIM Standby Threshold Voltage

0.2

0.3

V

FAULT PROTECTION

VCCUndervoltage Lockout

Threshold

Rising edge, hysteresis = 20mV, switching

disabled below this level

3.45

3.90

V

GATE DRIVERS

DH Gate-Driver On-Resistance

(Note 3)

RON(DH)

VBST- VLXforced to 5V

4.5

Ω

High state (pullup)

4.5

DL Gate-Driver On-Resistance

(Note 3)

RON(DL)

Low state (pulldown)

2.0

Ω

LOGIC

High

3.0

TRIG Logic Levels

VTRIG

350mV hysteresis

Low

1.2

V

Logic high (VCC; 200kHz operation)

VCC- 0.4

Open (300kHz operation)

1.6

3.1

TON Logic Levels

VTON

Logic low (GND; 550kHz operation)

0.5

V

Note 1: On-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST= 5V, and a 500pF

capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to

MOSFET switching speeds.

Note 2: The trigger delay time, tTRIG, is measured from the time the TRIG pin transitions to the time when the DL pin goes low.

Note 3: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN

package.

Note 4: The driver-disable delay time (tDD) is measured from the time the DD pin transitions to the time when the DL or DH pin tran-

sitions.

Note 5: Specifications to -40°C and +100°C are guaranteed by design and not production tested.