# 锁相环技术原理

## 鉴相器

u d ( t ) = u i ( t ) ∗ u o ( t ) = U i U o s i n ( ω i + θ i ) c o s ( ω o + θ o ) = K d s i n { [ ( ω i + ω o ) t + θ i + θ o ] } + s i n [ ( ω i − ω o ) t + θ i − θ o ] u_d(t) = u_i(t)*u_o(t)\\=U_iU_osin(\omega_i+\theta_i)cos(\omega_o+\theta_o)\\=K_dsin\left\{ \left[ (\omega_i+\omega_o)t+\theta_i+\theta_o \right] \right\}+sin\left[(\omega_i-\omega_o)t+\theta_i-\theta_o\right]

K d = 1 2 U i U o K_d = \frac{1}{2}U_iU_o

## 环路滤波器

### 一阶锁相环

F ( s ) = 1 K ω n F(s)=\frac{1}{K}\omega_n

### 二阶锁相环

F ( s ) = τ 2 s + 1 τ 1 s F(s)=\frac{\tau_2s+1}{\tau_1s}

ω n = ( K τ 1 ) 1 2 ξ = ω n τ 2 2 \omega_n=({\frac{K}{\tau_1}})^{\frac{1}{2}}\\\xi = \frac{\omega_n\tau_2}{2}

F ( s ) = 1 K ( 2 ξ ω n + ω n 2 s ) F(s)=\frac{1}{K}(2\xi\omega_n+\frac{\omega_n^2}{s})
a 2 = ξ a_2=\xi ，则表达式化简为：
F ( s ) = 1 K ( a 2 ω n + ω n 2 s ) F(s)=\frac{1}{K}(a_2\omega_n+\frac{\omega_n^2}{s})

### 三阶锁相环

F ( s ) = ( τ 2 s + 1 τ 1 s ) 2 F(s)=(\frac{\tau_2s+1}{\tau_1s})^2

F ( s ) = 1 K ( b 3 ω n + a 3 ω n 2 s + ω n 3 s ) F(s)=\frac{1}{K}(b_3\omega_n+\frac{a_3\omega_n^2 }{s}+\frac{\omega_n^3}{s})

b 3 = K f 3 ( K f 1 ) ( 1 3 ) , a 3 = K f 2 ( K f 1 ) ( 2 3 ) b_3=\frac{Kf_3}{(Kf_1)^(\frac{1}{3})},a_3=\frac{Kf_2}{(Kf_1)^(\frac{2}{3})}

## 压控振荡器

d ω o ( t ) d t = K o u f ( t ) \frac{d\omega_o(t)}{dt}=K_ou_f(t)
k o k_o 为压控振荡器的增益， ω o \omega_o 是输出信号的瞬时角频率，我们还可以得到振荡器输出信号的瞬间初始相位为：
θ o ( t ) = ∫ 0 t d ω o ( t ) d t d t = K o ∫ 0 t u f ( t ) d t \theta_o(t)=\int_0^t\frac{d\omega_o(t)}{dt}dt=K_o\int_0^tu_f(t)dt

V ( s ) = θ o ( s ) u f ( s ) = k o s V(s)=\frac{\theta_o(s)}{u_f(s)}=\frac{k_o}{s}

H ( s ) = θ o ( s ) θ i ( s ) = K F ( s ) s + K F ( s ) H(s)=\frac{\theta_o(s)}{\theta_i(s)}=\frac{KF(s)}{s+KF(s)}
F ( s ) F(s) 为环路滤波器的传递函数，K为系统总增益， K = K o K d K=K_oK_d

# 模拟锁相环数字化

## 从S域到Z域

Z变换也可以看作从拉普拉斯变换的采样，在设计数字环路滤波器的时候可以采用双线性变换积分器和矩形波积分器两种方式，将s离散化，具体形式如下：
s = 2 T 1 − z − 1 1 + z − 1 s = 1 − z ( − 1 ) T s=\frac{2}{T}\frac{1-z^{-1}}{1+z^{-1}}\\s=\frac{1-z^(-1)}{T}

## 稳态响应

lim ⁡ n → + ∞ θ e ( n ) = lim ⁡ z → 1 [ ( z − 1 ) θ e ( z ) ] θ e ( z ) = H e ( z ) θ i ( z ) {\lim_{n \to +\infty}}\theta_e(n)={\lim_{z \to 1}}\left[(z-1)\theta_e(z)\right]\\\theta_e(z)=H_e(z)\theta_i(z)
H(z)为系统函数, H e ( z ) H_e(z) 为误差信号系统函数

H ( z ) = T s ∑ n = 0 N − 1 b n z − n − 1 ( 1 − z − 1 ) N + T s ∑ n = 0 N − 1 b n z − n − 1 H(z)=\frac{T_s \sum_{n=0}^{N-1}b_nz^{-n-1}}{(1-z^{-1})^N+T_s \sum_{n=0}^{N-1}b_nz^{-n-1}}
H e ( z ) = 1 − H ( z ) = ( 1 − z − 1 ) N ( 1 − z − 1 ) N + T s ∑ n = 0 N − 1 b n z − n − 1 H_e(z)=1-H(z)=\frac{(1-z^{-1})^N}{(1-z^{-1})^N+T_s \sum_{n=0}^{N-1}b_nz^{-n-1}}

lim ⁡ n → ∞ θ e ( n ) = { Δ ω T s b 0 N = 1 0 N > 1 {\lim_{n \to \infty}}\theta_e(n)=\left\{ \begin{aligned} \frac{\Delta_\omega}{T_sb0} & & N=1 \\ 0 & &N>1 \\ \end{aligned} \right.

ξ \xi 越小，锁相环越灵敏， ω n \omega_n 越大，锁相环跟踪速度越快。

## 数控振荡器

M为相位增量控制字，N为数控振荡器的位数。

M = 2 N f o f c l k M=\frac{2^Nf_o}{f_{clk}}

## 相关参数计算

### 设计要求

1、输入PSK信号量化位宽：10bit
2、数控振荡器输出复制载波信号位宽：10bit
3、系统时钟60Mhz
4、输入PSK信号码率4Mhz，载波66Mhz
5、数控振荡器位宽32bit
6、鉴相器低通滤波器量化位宽为12bit

### 输入信号

f c = R s ( 1 + α ) 2 = 3.6 M h z f_c=\frac{R_s(1+\alpha)}{2}=3.6Mhz

### 鉴相器

K d = 1 2 U i U o K_d=\frac{1}{2}U_iU_o 故输出的最大值为 1 2 2 9 2 9 = 2 17 \frac{1}{2}2^92^9=2^{17}

ϕ e = a r c t a n ( Q I ) ϕ e = Q I ϕ e = Q I ϕ e = Q ∗ s i g n ( I ) \phi_e=arctan(\frac{Q}{I})\\ \phi_e=\frac{Q}{I}\\ \phi_e=QI\\ \phi_e=Q*sign(I) 采用最后一种方法不增加位宽，因此采用了自后一种方法来通过IQ两路计算信号相位差。

fs = 30e6;
fc = [3.6e6 8.4e6];
mag=[1 0];
dev=[0.04 0.01];
[n,wn,beta,ftype] = kaiserord(fc,mag,dev,fs);
fpm = [0 fc(1)*2/fs fc(2)*2/fs 1];
magpm = [1 1 0 0]
format long;
h_pm = firpm(n,fpm,magpm);

qm = 12;
q = round(h_pm/max(abs(h_pm))*(2^(qm-1)-1));
s_q = sum(abs(q));
scale = max(abs(q))/max(abs(h_pm))

scale求出了量化带来的增益。求滤波器的幅频响应曲线为：

K d = 2 17 ∗ 5144 K_d=2^{17}*5144

### 数控振荡器

k o = 2 π f c l k T n c o 2 32 k_o=\frac{2\pi f_{clk}T_{nco}}{2^{32}}
M = 2 32 f o f c l k = 858993459 M=\frac{2^{32}f_{o}}{f_{clk}}=858993459

K = K d K o = 2 17 ∗ 5144 ∗ 2 π 2 32 = 0.9858 K=K_dK_o=\frac{2^{17}*5144*2\pi}{2^{32}}=0.9858

### 环路滤波器

ξ = 0.7071 \xi=0.7071 ω n = 0.5 M h z \omega_n=0.5Mhz

C 1 = 2 − 6 C 2 = 2 − 12 C_1=2^{-6}\\ C_2=2^{-12}

# FPGA实现二阶、三阶锁相环

## 鉴相器部分

    mult_gen_0 mq(
.clk(clk),
.a(din),
.b(cosine),
.p(mdq)
);
mult_gen_0 mi(
.clk(clk),
.a(din),
.b(sine),
.p(mdi)
);

    fir_compiler_0 fq(
.aclk(clk),
.s_axis_data_tdata(mdq[18:0]),
.s_axis_data_tvalid(1'b1),
.m_axis_data_tdata(dq),
.m_axis_data_tvalid(m_axis_data_tvalid_q)
);
fir_compiler_0 fi(
.aclk(clk),
.s_axis_data_tdata(mdi[18:0]),
.s_axis_data_tvalid(1'b1),
.m_axis_data_tdata(di),
.m_axis_data_tvalid(m_axis_data_tvalid_i)
);

module phase_detect(rst,clk,di,dq,pd);
input rst;
input clk;
input signed[31:0]di;
input signed[31:0]dq;
output signed[31:0]pd;
reg signed [31:0]pdout;
always@(posedge clk or posedge rst)
if(!rst)
pdout <= 32'd0;
else
begin
if(di[31])
pdout <= -dq;
else
pdout <= dq;
end
assign pd = pdout;
endmodule

## 环路滤波器部分

module filter_loop(rst,clk,pd,frequency_df);
input rst;
input clk;
input signed[31:0]pd;
output signed[31:0]frequency_df;
reg signed[31:0]sum_d;
wire signed[31:0]pd_c2,pd_c1,sum;
wire signed[31:0]df;
assign pd_c1 = {{6{pd[31]}},pd[31:6]};
assign pd_c2 = {{12{pd[31]}},pd[31:12]};
always@(posedge clk or posedge rst)
if(!rst)
sum_d <= 0;
else
sum_d <= sum;
assign sum = pd_c2+sum_d;
assign df = sum_d+pd_c1;
assign frequency_df = df;
endmodule

## 数控振荡器部分

    assign carrier = 32'd809332900;
assign s_axis_config_tdata = frequency_df + carrier;
dds_compiler_0 dd1(
.aclk(clk),
.aresetn(rst),
.s_axis_config_tdata(s_axis_config_tdata),
.s_axis_config_tvalid(1'b1),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(m_axis_phase_tdata),
.m_axis_phase_tvalid(m_axis_phase_tvalid)
);
wire signed[9:0]cosine;
wire signed[9:0]sine;
assign cosine = m_axis_data_tdata[9:0];
assign sine = m_axis_data_tdata[25:16];

## 总模块

module PLL_TWO(
rst,clk,din,datai,dataq,pd,frequency_df
);
input rst;
input clk;
input signed[9:0]din;
output signed[31:0]datai;
output signed[31:0]dataq;
output signed[31:0]pd;
output signed[31:0]frequency_df;
wire signed[31:0] s_axis_config_tdata;
wire signed[31:0] m_axis_data_tdata;//sine and cosine
wire m_axis_data_tvalid;
wire m_axis_phase_tvalid;
wire signed[31:0] m_axis_phase_tdata;
wire signed[31:0] carrier;
assign carrier = 32'd809332900;
assign s_axis_config_tdata = frequency_df + carrier;
dds_compiler_0 dd1(
.aclk(clk),
.aresetn(rst),
.s_axis_config_tdata(s_axis_config_tdata),
.s_axis_config_tvalid(1'b1),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(m_axis_phase_tdata),
.m_axis_phase_tvalid(m_axis_phase_tvalid)
);
wire signed[9:0]cosine;
wire signed[9:0]sine;
assign cosine = m_axis_data_tdata[9:0];
assign sine = m_axis_data_tdata[25:16];
wire signed[19:0]mdq;
wire signed[19:0]mdi;
mult_gen_0 mq1(
.CLK(clk),
.A(din),
.B(cosine),
.P(mdq)
);
mult_gen_0 mi1(
.CLK(clk),
.A(din),
.B(sine),
.P(mdi)
);
wire signed[31:0]dq;
wire signed[31:0]di;
wire m_axis_data_tvalid_q;
wire m_axis_data_tvalid_i;
fir_compiler_0 fq(
.aclk(clk),
.s_axis_data_tdata(mdq[18:0]),
.s_axis_data_tvalid(1'b1),
.m_axis_data_tdata(dq),
.m_axis_data_tvalid(m_axis_data_tvalid_q)
);
fir_compiler_0 fi(
.aclk(clk),
.s_axis_data_tdata(mdi[18:0]),
.s_axis_data_tvalid(1'b1),
.m_axis_data_tdata(di),
.m_axis_data_tvalid(m_axis_data_tvalid_i)
);
wire signed[31:0]pd;
phase_detect ph1(
.rst(rst),
.clk(clk),
.di(di),
.dq(dq),
.pd(pd)
);
wire signed[31:0]frequency_df;
filter_loop f1(
.rst(rst),
.clk(clk),
.pd(pd),
.frequency_df(frequency_df)
);
assign datai = di;
assign dataq = dq;
endmodule

## 仿真测试

pd为鉴相器的输出，即输出信号与输入信号的相位差异。
frequency_df为环路滤波器的输出。从图中可以看出，在第九百个周期左右锁相环达到锁定状态。

## 三阶锁相环

F ( z ) = C 1 + C 2 z − 1 1 − z − 1 + C 3 ( z − 1 1 − z − 1 ) 2 C 1 = b 3 ω n T K C 2 = a 3 ω n 2 T 2 K C 3 = ω n 3 T 3 K F(z)=C_1+C_2\frac{z^{-1}}{1-z^{-1}}+C_3(\frac{z^{-1}}{1-z^{-1}})^2\\ C_1=\frac{b_3\omega_nT}{K}\\ C_2 = \frac{a_3\omega_n^2T^2}{K}\\ C_3=\frac{\omega_n^3T^3}{K} a 3 = 1.1 , b 3 = 2.4 , ω n = 0.5 M h z a_3=1.1,b_3=2.4,\omega_n=0.5Mhz 可以求出三阶锁相环的环路滤波器参数 C 1 , C 2 , C 3 C_1,C_2,C_3 ，从而在FPGA中进行相对应的移位操作，具体原理公式上面有写，计算结果如下：
C 1 = 2 − 5 C 2 = 2 − 12 C 3 = 2 − 18 C_1=2^{-5}\\ C_2=2^{-12}\\ C_3=2^{-18}

module filter_loop(rst,clk,pd,frequency_df);
input rst;
input clk;
input signed[31:0]pd;
output signed[31:0]frequency_df;
reg signed[31:0]sum_c2,sum_c3,sum_c3_2;
wire signed[31:0]pd_c2,pd_c1,pd_c3,sum_2,sum_3;
wire signed[31:0]df;
assign pd_c1 = {{5{pd[31]}},pd[31:5]};
assign pd_c2 = {{12{pd[31]}},pd[31:12]};
assign pd_c3 = {{18{pd[31]}},pd[31:18]};
always@(posedge clk or posedge rst)
if(!rst)
begin
sum_c2 <= 0;
sum_c3 <= 0;
sum_c3_2 <= 0;
end
else
begin
sum_c2 <= sum_2;
sum_c3 = sum_c3_2;
sum_c3_2 = sum_3;
end
assign sum_2 = pd_c2+sum_c2;
assign sum_3 = pd_c3-sum_c3+2*sum_c3_2;
assign df = sum_c2+pd_c1+sum_c3;
assign frequency_df = df;
endmodule

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