always @(posedge sys_clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
clk_out <= 0;
data_cnt03<=4'd0;
end
else begin
if(data_cnt03<4'd8)begin
data_cnt03<=data_cnt03+1'b1;
end
else begin
clk_out <= ~clk_out;
data_cnt03<=4'd0;
end
end
end
标题##状态的自我维持always @(posedge sys_clk or negedge rst_n) begin if(rst_n == 1'b0) begin clk_out <= 0; data_cnt03<=4'd0; end else begin if(data_cnt03<4'd8)begin data_cnt03<=data_cnt03+1'b1; e