HDLBits学习记录-1

HDLBits 新手解决方案

[Edgecapture]

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问题

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

说明

该问题是需要检测下降沿，并保持检测状态直至reset信号有效，同时，注意同步复位；

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] nedge;
    always @ (posedge clk) begin
          nedge <= in;
        if (reset)
            out <= 0;
        else 
           out <= nedge & (~in)|out;//注意保持寄存器操作需要对上一个out进行或操作
    end       

endmodule

总结