interface.sv

interface ahb_if(input    hclk);

logic    hrst_n;
logic    hclk;
logic    hsel;
logic    hready;
logic    hwrite;
logic[1:0]    htrans;
logic[2:0]    hburst;
logic[2:0]    hsize;
logic[31:0]   haddr;
logic[31:0]   hwdata;
logic[31:0]   hrdata;

clocking drv_cb@(posedge hclk);
    output    hsel;
    output    hready;
    output    hwrite;
    output    htrans;
    output    hburst;
    output    hsize;
    output    haddr;
    output    hwdata;
    input     hrdata;
endclocking

clocking mon_cb@(posedge hclk);
    input    hsel;
    input    hready;
    input    hwrite;
    input    htrans;
    input    hburst;
    input    hsize;
    input    haddr;
    input    hwdata;
    input    hrdata;
endclocking

modport driver(clocking drv_cb);
modport monitor(clocking mon_cb);

endinterface