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文章目录
- 目标
- ATPG Test Pattern Types
- Basic Scan Patterns—Review
- Clock Sequential Patterns
- Clock Sequential Pattern Operation
- Clock PO Patterns
- Traditional: Testing Around RAMs
- Structured Test With RAMs
- Elements of a RAM
- Control Signals for RAMs
- Multiple Load (Multi-Load) Patterns
- Example: Using Multi-Load Patterns to Test RAMs
- Example2: Using Multi-Load Patterns for Test(Cont.)
- Generating Optimum Test Patterns
- Report Patterns
- Example 1: Report Scan Cells
- Labeling Memory Elements in report_scan_cells
- Scan Cell lnversion Flags
- Writing Patterns
- overview: Time-Based Verification
- Time-Based Verification: TestBench Creation
- Time-Based Verification (Change Pattern Timing)
- Manufacturing Test Patterns
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目标
Upon completion of this module, you should be able to:
- Describe various ATPG pattern types that are created.
- Describe why each type is needed.
- Apply techniques to improve test coverage.
完成此模块后，您应该能够：
- 描述所创建的各种ATPG模式类型。
- 说明为什么需要每种类型。
- 应用技术来提高测试覆盖率。
ATPG Test Pattern Types
Tessent Shell (running Tessent FastScan orTessent TestKompress)generates thefollowing test pattern types:
- Basic Scan
- Used on full-scan design circuitry
- Clock Sequential
- Used to propagate values through non-scan latches and DFFs with limited sequential depth
- A series of functional cycles after load
- Clock PO
- Used on circuitry where a clock signal passes through combi
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