Write a Verilog test bench that goes through every possible input, and for each input

Write a Verilog test bench that goes through every possible input, and for each input, prints out either “match” or “mismatch” depending on whether the above two modules produce the same or different output.

Expert Solution
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Step 1

1. Add module definition.
2. Declare port.
3. internal wire declaration.
4. gate instantiations.

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Step 2
// module definition
module AOI(A, B, C, D, Y);
// port declaration
input A, B, C;
output D;
// internal wireing declaration
wire E, F;
// instantiations to gate
or or1(E, A, B);
and and1(F, B, C);
nand nand1(D, E, F);
endmodule