仿真结果
设计文件程序
module led_flashself(
input Clk,
input Reset_n,
output reg Led
);
reg [24:0] counter;
parameter MCNT = 25'd24999999;
always@(posedge Clk or negedge Reset_n)begin
if(!Reset_n)
counter <= 0;
else if(counter == MCNT)
counter <= 0;
else
counter <= counter + 1'd1;
end
always@(posedge Clk or negedge Reset_n)begin
if(!Reset_n)
Led <= 0;
else if(counter == MCNT)
Led <= !Led;
end
endmodule
module led_flashself_test(
input Clk,
input Reset_n,
output [4:0] Led
);
led_flashself led_flashself_0(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led[0])
);
defparam led_flashself_0.MCNT = 25'd24999999;
led_flashself led_flashself_1(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led[1])
);
defparam led_flashself_1.MCNT = 25'd2499999;
led_flashself led_flashself_2(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led[2])
);
defparam led_flashself_2.MCNT = 25'd4999999;
led_flashself led_flashself_3(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led[3])
);
defparam led_flashself_3.MCNT = 25'd7499999;
led_flashself led_flashself_4(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led[4])
);
defparam led_flashself_4.MCNT = 25'd9999999;
endmodule
仿真文件程序
`timescale 1ns/1ns
module led_flashself_tb();
reg Clk;
reg Reset_n;
wire [4:0]Led;
led_flashself_test led_flashself_sim(
.Clk(Clk),
.Reset_n(Reset_n),
.Led(Led)
);
initial Clk <= 0;
always #20 Clk <= !Clk;
initial begin
Reset_n <= 0;
#200;
Reset_n <= 1;
#2000000;
end
endmodule