FPGA入门学习笔记（十九）Vivado设计VGA控制器

NonnettaWu

已于 2023-05-17 20:06:13 修改

阅读量487

点赞数

分类专栏： FPGA 文章标签： fpga开发学习

于 2023-04-07 17:10:57 首次发布

本文链接：https://blog.csdn.net/weixin_45463952/article/details/130004318

版权

FPGA 专栏收录该内容

21 篇文章 15 订阅

订阅专栏

该文描述了一个使用Verilog编写的VGA控制器模块，该模块处理时钟、复位信号以及数据输入，生成水平同步(VGA_HS)、垂直同步(VGA_VS)信号，并根据预定义的边界条件决定数据请求(Data_Req)和显示RGB数据。同时提供了一个测试模块VGA_CTRL_tb用于验证其功能。

摘要由CSDN通过智能技术生成

仿真波形

在这里插入图片描述

设计文件程序

`timescale 1ns/1ns
module VGA_CTRL(
        Clk,
        Reset_N,
        Data,
        Data_Req,
        VGA_HS,
        VGA_VS,
        VGA_BLK,
        VGA_RGB
    );
    input Clk;
    input Reset_N;
    input [23:0]Data;
    output reg Data_Req;
    output reg VGA_HS;
    output reg VGA_VS;
    output reg VGA_BLK;
    output reg [23:0]VGA_RGB; // {Red:[7:0],Green:[7:0],Blue:[7:0]}
    
    localparam Hsync_End = 1344;
    localparam Hs_End = 136;
    localparam Vsync_End = 628;
    localparam Vs_End = 4;
    localparam Hdata_Begin = 296;
    localparam Hdata_End = 1320;
    localparam Vdata_Begin = 27;
    localparam Vdata_End = 627;
    
    reg [11:0]H_cnt;
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        H_cnt <= 0;
    else if(H_cnt >= Hsync_End - 1)
        H_cnt <= 0;
    else
        H_cnt <= H_cnt + 1'b1;

    always@(posedge Clk)
        VGA_HS <= (H_cnt < Hs_End)?0:1;
    
    reg [11:0]V_cnt;
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        V_cnt <= 0;
    else if(H_cnt == Hsync_End - 1)begin
        if(V_cnt >= Vsync_End - 1)
            V_cnt <= 0;
        else
            V_cnt <= V_cnt + 1'b1;
    end
    
    always@(posedge Clk)
        VGA_VS <= (V_cnt < Vs_End)?0:1; 
    
    always@(posedge Clk)
        Data_Req <= ((H_cnt >= Hdata_Begin - 1'd1) && (H_cnt < Hdata_End -1'd1) && (V_cnt >= Vdata_Begin) && (V_cnt < Vdata_End - 1'd1))?1:0;

    //BLK表示数据有效输出的时间段
    always@(posedge Clk)
        VGA_BLK <= Data_Req;

    always@(posedge Clk)    
        VGA_RGB <= Data_Req?Data:0;
    
endmodule

仿真文件程序

`timescale 1ns / 1ns

module VGA_CTRL_tb();
    reg Clk;
    reg Reset_N;
    reg [23:0]Data;
    wire Data_Req;
    wire VGA_HS;
    wire VGA_VS;
    wire VGA_BLK;
    wire [23:0]VGA_RGB;

    VGA_CTRL VGA_CTRL(
        Clk,
        Reset_N,
        Data,
        Data_Req,
        VGA_HS,
        VGA_VS,
        VGA_BLK,
        VGA_RGB
    );
    initial Clk = 0;
    always #20 Clk = !Clk;
    initial begin
        Reset_N = 0;
        #201;
        Reset_N = 1;
        #2000000;
        $stop;
    end
    
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        Data <= 0;
    else if(!Data_Req)
        Data <= Data;
    else
        Data <= Data + 1'b1;
endmodule