MIG控制器破解（1）：phy_control_001.vp破解（verilog）

已于 2024-12-08 17:25:44 修改
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分类专栏： IC逆向设计 文章标签： fpga开发 DDR控制器 PHY破解
于 2024-09-12 12:40:20 首次发布
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本文链接：https://blog.csdn.net/weixin_46423500/article/details/142172336
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XILINX MIG控制器结构：

1	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/BUFG.v
2	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/BUFH.v
3	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/PLLE2_ADV.v
4	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IDELAYCTRL.v
5	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/MMCME2_ADV.v
6	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/retarget/IBUFGDS.v
7	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/RAM32M.v
8	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/SRLC32E.v
9	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/OBUF.v
10	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/OBUFT.v
11	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/ODDR.v
12	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/OBUFDS.v
13	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/ISERDESE2.v
14	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/OSERDESE2.v
15	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IBUFDS.v
16	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/BUFIO.v
17	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IOBUF_INTERMDISABLE.v
18	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IOBUFDS_INTERMDISABLE.v
19	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/XADC.v
20	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IDELAYE2.v
21	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/PHY_CONTROL.v
22	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/PHASER_REF.v
23	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/PHASER_IN_PHY.v
24	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/PHASER_OUT_PHY.v
25	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/IN_FIFO.v
26	/tools/Xilinx2022.2/Vivado/2022.2/data/verilog/src/unisims/OUT_FIFO.v

完整代码压缩包会在最后一章节上传。
DDR控制器MIG底层硬件逻辑：

phy_control_001文件模块解码：

`timescale 1ps / 1ps

module sip_phy_control
(
input [3:0] ao_toggle,
input [3:0] ao_wrlvl_en,
input burst_mode,
input [2:0] clk_ratio,
input [5:0] cmd_offset,
input [2:0] co_duration,
input data_ctl_a_n,
input data_ctl_b_n,
input data_ctl_c_n,
input data_ctl_d_n,
input [2:0] di_duration,
input disable_seq_match,
input [2:0] do_duration,
input [5:0] events_delay,
input [5:0] four_window_clocks,
input multi_region,
input phy_count_enable,
input [5:0] rd_cmd_offset_0,
input [5:0] rd_cmd_offset_1,
input [5:0] rd_cmd_offset_2,
input [5:0] rd_cmd_offset_3,
input [5:0] rd_duration_0,
input [5:0] rd_duration_1,
input [5:0] rd_duration_2,
input [5:0] rd_duration_3,
input spare,
input sync_mode,
input [5:0] wr_cmd_offset_0,
input [5:0] wr_cmd_offset_1,
input [5:0] wr_cmd_offset_2,
input [5:0] wr_cmd_offset_3,
input [5:0] wr_duration_0,
input [5:0] wr_duration_1,
input [5:0] wr_duration_2,
input [5:0] wr_duration_3,

output [3:0] auxoutput,
output [3:0] inburstpending,
output [1:0] inranka,
output [1:0] inrankb,
output [1:0] inrankc,
output [1:0] inrankd,
output [3:0] outburstpending,
output [1:0] pcenablecalib,
output phyctlalmostfull,
output phyctlempty,
output phyctlfull,
output phyctlready,
output [15:0] testoutput,
input memrefclk,
input phyclk,
input phyctlmstrempty,
input [31:0] phyctlwd,
input phyctlwrenable,
input plllock,
input readcalibenable,
input refdlllock,
input reset,
input scanenablen,
input syncin,
input [15:0] testinput,
input [2:0] testselect,
input writecalibenable,
input gsr
);

//protect begin

// (no unconnected output in this block)

// global signal declarations

wire _cfg_reset = global_events.cfg_reset;
wire _ghigh_b = global_events.ghigh_b;
wire _grestore = global_events.grestore;
wire _gwe = global_events.gwe;

// (no supply1 signals in this block)

// (no supply0 signals in this block)

// (no mcaddr signals in this block)

// (no mcdata signals in this block)

// interconnect signal declarations

wire [3:0] _Aux_Output_N;
wire [3:0] _In_Burst_Pending;
wire [1:0] _In_Rank_A;
wire [1:0] _In_Rank_B;
wire [1:0] _In_Rank_C;
wire [1:0] _In_Rank_D;
wire [3:0] _MC_AO_TOGGLE;
wire [3:0] _MC_AO_WRLVL_EN;
wire _MC_BURST_MODE;
wire [2:0] _MC_CLK_RATIO;
wire [5:0] _MC_CMD_OFFSET;
wire [2:0] _MC_CO_DURATION;
wire _MC_DATA_CTL_A_N;
wire _MC_DATA_CTL_B_N;
wire _MC_DATA_CTL_C_N;
wire _MC_DATA_CTL_D_N;
wire [2:0] _MC_DI_DURATION;
wire _MC_DISABLE_SEQMATCH;
wire [2:0] _MC_DO_DURATION;
wire [5:0] _MC_EVENTS_DELAY;
wire _MC_MULTI_REGION;
wire _MC_PHY_CNT_ENAB;
wire [5:0] _MC_RD_CMD_OFFSET_0;
wire [5:0] _MC_RD_CMD_OFFSET_1;
wire [5:0] _MC_RD_CMD_OFFSET_2;
wire [5:0] _MC_RD_CMD_OFFSET_3;
wire [5:0] _MC_RD_DURATION_0;
wire [5:0] _MC_RD_DURATION_1;
wire [5:0] _MC_RD_DURATION_2;
wire [5:0] _MC_RD_DURATION_3;
wire _MC_SPARE;
wire _MC_SYNC_MODE;
wire [5:0] _MC_WR_CMD_OFFSET_0;
wire [5:0] _MC_WR_CMD_OFFSET_1;
wire [5:0] _MC_WR_CMD_OFFSET_2;
wire [5:0] _MC_WR_CMD_OFFSET_3;
wire [5:0] _MC_WR_DURATION_0;
wire [5:0] _MC_WR_DURATION_1;
wire [5:0] _MC_WR_DURATION_2;
wire [5:0] _MC_WR_DURATION_3;
wire [5:0] _MC_4WINDOW_CLKS;
wire _Mem_Ref_Clk;
wire [3:0] _Out_Burst_Pending;
wire [1:0] _PC_Enable_Calib;
wire _PHY_Clk;
wire _PHY_Ctl_AlmostFull_N;
wire _PHY_Ctl_Empty;
wire _PHY_Ctl_Full_N;
wire _PHY_Ctl_Mstr_Empty;
wire _PHY_Ctl_Ready_N;
wire [31:0] _PHY_Ctl_Wd;
wire _PHY_Ctl_Wr_Enable;
wire _PLL_Lock;
wire _Read_Calib_Enable;
wire _RefDLL_Lock;
wire _Reset;
wire _Scan_Enable_N;
wire _Sync_In;
wire [15:0] _Test_Input;
wire [15:0] _Test_Output_N;
wire [2:0] _Test_Select;
wire _Write_Calib_Enable;

// (no optinv attribute in this block)

// (no cfg_const attribute in this block)

// (no software attribute memory cell macro in this block)

// (no optinv attribute memory cell macro in this block)

// (no cfg_const attribute memory cell macro in this block)

// (no programming attribute memory cell macro in this block)

// (no optinv attribute in this block)

// (no cfg_const attribute in this block)

// assign netlist module input (and inout) pins

assign _Mem_Ref_Clk = MEMREFCLK;
assign _PHY_Clk = _ghigh_b ? PHYCLK : 1’b1;
assign _PHY_Ctl_Mstr_Empty = _ghigh_b ? PHYCTLMSTREMPTY : 1’b1;
assign _PHY_Ctl_Wd[0] = _ghigh_b ? PHYCTLWD[0] : 1’b1;
assign _PHY_Ctl_Wd[1] = _ghigh_b ? PHYCTLWD[1] : 1’b1;
assign _PHY_Ctl_Wd[2] = _ghigh_b ? PHYCTLWD[2] : 1’b1;
assign _PHY_Ctl_Wd[3] = _ghigh_b ? PHYCTLWD[3] : 1’b1;
assign _PHY_Ctl_Wd[4] = _ghigh_b ? PHYCTLWD[4] : 1’b1;
assign _PHY_Ctl_Wd[5] = _ghigh_b ? PHYCTLWD[5] : 1’b1;
assign _PHY_Ctl_Wd[6] = _ghigh_b ? PHYCTLWD[6] : 1’b1;
assign _PHY_Ctl_Wd[7] = _ghigh_b ? PHYCTLWD[7] : 1’b1;
assign _PHY_Ctl_Wd[8] = _ghigh_b ? PHYCTLWD[8] : 1’b1;
assign _PHY_Ctl_Wd[9] = _ghigh_b ? PHYCTLWD[9] : 1’b1;
assign _PHY_Ctl_Wd[10] = _ghigh_b ? PHYCTLWD[10] : 1’b1;
assign _PHY_Ctl_Wd[11] = _ghigh_b ? PHYCTLWD[11] : 1’b1;
assign _PHY_Ctl_Wd[12] = _ghigh_b ? PHYCTLWD[12] : 1’b1;
assign _PHY_Ctl_Wd[13] = _ghigh_b ? PHYCTLWD[13] : 1’b1;
assign _PHY_Ctl_Wd[14] = _ghigh_b ? PHYCTLWD[14] : 1’b1;
assign _PHY_Ctl_Wd[15] = _ghigh_b ? PHYCTLWD[15] : 1’b1;
assign _PHY_Ctl_Wd[16] = _ghigh_b ? PHYCTLWD[16] : 1’b1;
assign _PHY_Ctl_Wd[17] = _ghigh_b ? PHYCTLWD[17] : 1’b1;
assign _PHY_Ctl_Wd[18] = _ghigh_b ? PHYCTLWD[18] : 1’b1;
assign _PHY_Ctl_Wd[19] = _ghigh_b ? PHYCTLWD[19] : 1’b1;
assign _PHY_Ctl_Wd[20] = _ghigh_b ? PHYCTLWD[20] : 1’b1;
assign _PHY_Ctl_Wd[21] = _ghigh_b ? PHYCTLWD[21] : 1’b1;
assign _PHY_Ctl_Wd[22] = _ghigh_b ? PHYCTLWD[22] : 1’b1;
assign _PHY_Ctl_Wd[23] = _ghigh_b ? PHYCTLWD[23] : 1’b1;
assign _PHY_Ctl_Wd[24] = _ghigh_b ? PHYCTLWD[24] : 1’b1;
assign _PHY_Ctl_Wd[25] = _ghigh_b ? PHYCTLWD[25] : 1’b1;
assign _PHY_Ctl_Wd[26] = _ghigh_b ? PHYCTLWD[26] : 1’b1;
assign _PHY_Ctl_Wd[27] = _ghigh_b ? PHYCTLWD[27] : 1’b1;
assign _PHY_Ctl_Wd[28] = _ghigh_b ? PHYCTLWD[28] : 1’b1;
assign _PHY_Ctl_Wd[29] = _ghigh_b ? PHYCTLWD[29] : 1’b1;
assign _PHY_Ctl_Wd[30] = _ghigh_b ? PHYCTLWD[30] : 1’b1;
assign _PHY_Ctl_Wd[31] = _ghigh_b ? PHYCTLWD[31] : 1’b1;
assign _PHY_Ctl_Wr_Enable = _ghigh_b ? PHYCTLWRENABLE : 1’b1;
assign _PLL_Lock = _ghigh_b ? PLLLOCK : 1’b1;
assign _Read_Calib_Enable = _ghigh_b ? READCALIBENABLE : 1’b1;
assign _RefDLL_Lock = _ghigh_b ? REFDLLLOCK : 1’b1;
assign _Reset = _ghigh_b ? RESET : 1’b1;
assign _Scan_Enable_N = _ghigh_b ? SCANENABLEN : 1’b1;
assign _Sync_In = SYNCIN;
assign _Test_Input[0] = _ghigh_b ? TESTINPUT[0] : 1’b1;
assign _Test_Input[1] = _ghigh_b ? TESTINPUT[1] : 1’b1;
assign _Test_Input[2] = _ghigh_b ? TESTINPUT[2] : 1’b1;
assign _Test_Input[3] = _ghigh_b ? TESTINPUT[3] : 1’b1;
assign _Test_Input[4] = _ghigh_b ? TESTINPUT[4] : 1’b1;
assign _Test_Input[5] = _ghigh_b ? TESTINPUT[5] : 1’b1;
assign _Test_Input[6] = _ghigh_b ? TESTINPUT[6] : 1’b1;
assign _Test_Input[7] = _ghigh_b ? TESTINPUT[7] : 1’b1;
assign _Test_Input[8] = _ghigh_b ? TESTINPUT[8] : 1’b1;
assign _Test_Input[9] = _ghigh_b ? TESTINPUT[9] : 1’b1;
assign _Test_Input[10] = _ghigh_b ? TESTINPUT[10] : 1’b1;
assign _Test_Input[11] = _ghigh_b ? TESTINPUT[11] : 1’b1;
assign _Test_Input[12] = _ghigh_b ? TESTINPUT[12] : 1’b1;
assign _Test_Input[13] = _ghigh_b ? TESTINPUT[13] : 1’b1;
assign _Test_Input[14] = _ghigh_b ? TESTINPUT[14] : 1’b1;
assign _Test_Input[15] = _ghigh_b ? TESTINPUT[15] : 1’b1;
assign _Test_Select[0] = _ghigh_b ? TESTSELECT[0] : 1’b1;
assign _Test_Select[1] = _ghigh_b ? TESTSELECT[1] : 1’b1;
assign _Test_Select[2] = _ghigh_b ? TESTSELECT[2] : 1’b1;
assign _Write_Calib_Enable = _ghigh_b ? WRITECALIBENABLE : 1’b1;

// assign netlist module output (and inout) pins

assign AUXOUTPUT[0] = ~_Aux_Output_N[0];
assign AUXOUTPUT[1] = ~_Aux_Output_N[1];
assign AUXOUTPUT[2] = ~_Aux_Output_N[2];
assign AUXOUTPUT[3] = ~_Aux_Output_N[3];
assign INBURSTPENDING[0] = _In_Burst_Pending[0];
assign INBURSTPENDING[1] = _In_Burst_Pending[1];
assign INBURSTPENDING[2] = _In_Burst_Pending[2];
assign INBURSTPENDING[3] = _In_Burst_Pending[3];
assign INRANKA[0] = _In_Rank_A[0];
assign INRANKA[1] = _In_Rank_A[1];
assign INRANKB[0] = _In_Rank_B[0];
assign INRANKB[1] = _In_Rank_B[1];
assign INRANKC[0] = _In_Rank_C[0];
assign INRANKC[1] = _In_Rank_C[1];
assign INRANKD[0] = _In_Rank_D[0];
assign INRANKD[1] = _In_Rank_D[1];
assign OUTBURSTPENDING[0] = _Out_Burst_Pending[0];
assign OUTBURSTPENDING[1] = _Out_Burst_Pending[1];
assign OUTBURSTPENDING[2] = _Out_Burst_Pending[2];
assign OUTBURSTPENDING[3] = _Out_Burst_Pending[3];
assign PCENABLECALIB[0] = _PC_Enable_Calib[0];
assign PCENABLECALIB[1] = _PC_Enable_Calib[1];
assign PHYCTLALMOSTFULL = ~_PHY_Ctl_AlmostFull_N;
assign PHYCTLEMPTY = _PHY_Ctl_Empty;
assign PHYCTLFULL = ~_PHY_Ctl_Full_N;
assign PHYCTLREADY = ~_PHY_Ctl_Ready_N;
assign TESTOUTPUT[0] = ~_Test_Output_N[0];
assign TESTOUTPUT[1] = ~_Test_Output_N[1];
assign TESTOUTPUT[2] = ~_Test_Output_N[2];
assign TESTOUTPUT[3] = ~_Test_Output_N[3];
assign TESTOUTPUT[4] = ~_Test_Output_N[4];
assign TESTOUTPUT[5] = ~_Test_Output_N[5];
assign TESTOUTPUT[6] = ~_Test_Output_N[6];
assign TESTOUTPUT[7] = ~_Test_Output_N[7];
assign TESTOUTPUT[8] = ~_Test_Output_N[8];
assign TESTOUTPUT[9] = ~_Test_Output_N[9];
assign TESTOUTPUT[10] = ~_Test_Output_N[10];
assign TESTOUTPUT[11] = ~_Test_Output_N[11];
assign TESTOUTPUT[12] = ~_Test_Output_N[12];
assign TESTOUTPUT[13] = ~_Test_Output_N[13];
assign TESTOUTPUT[14] = ~_Test_Output_N[14];
assign TESTOUTPUT[15] = ~_Test_Output_N[15];

// assign software attribute configured pins

assign _MC_AO_TOGGLE[3] = AO_TOGGLE[3];
assign _MC_AO_TOGGLE[2] = AO_TOGGLE[2];
assign _MC_AO_TOGGLE[1] = AO_TOGGLE[1];
assign _MC_AO_TOGGLE[0] = AO_TOGGLE[0];
assign _MC_AO_WRLVL_EN[3] = AO_WRLVL_EN[3];
assign _MC_AO_WRLVL_EN[2] = AO_WRLVL_EN[2];
assign _MC_AO_WRLVL_EN[1] = AO_WRLVL_EN[1];
assign _MC_AO_WRLVL_EN[0] = AO_WRLVL_EN[0];
assign _MC_BURST_MODE = BURST_MODE;
assign _MC_CLK_RATIO[2] = CLK_RATIO[2];
assign _MC_CLK_RATIO[1] = CLK_RATIO[1];
assign _MC_CLK_RATIO[0] = CLK_RATIO[0];
assign _MC_CMD_OFFSET[5] = CMD_OFFSET[5];
assign _MC_CMD_OFFSET[4] = CMD_OFFSET[4];
assign _MC_CMD_OFFSET[3] = CMD_OFFSET[3];
assign _MC_CMD_OFFSET[2] = CMD_OFFSET[2];
assign _MC_CMD_OFFSET[1] = CMD_OFFSET[1];
assign _MC_CMD_OFFSET[0] = CMD_OFFSET[0];
assign _MC_CO_DURATION[2] = CO_DURATION[2];
assign _MC_CO_DURATION[1] = CO_DURATION[1];
assign _MC_CO_DURATION[0] = CO_DURATION[0];
assign _MC_DATA_CTL_A_N = DATA_CTL_A_N;
assign _MC_DATA_CTL_B_N = DATA_CTL_B_N;
assign _MC_DATA_CTL_C_N = DATA_CTL_C_N;
assign _MC_DATA_CTL_D_N = DATA_CTL_D_N;
assign _MC_DI_DURATION[2] = DI_DURATION[2];
assign _MC_DI_DURATION[1] = DI_DURATION[1];
assign _MC_DI_DURATION[0] = DI_DURATION[0];
assign _MC_DISABLE_SEQMATCH = DISABLE_SEQ_MATCH;
assign _MC_DO_DURATION[2] = DO_DURATION[2];
assign _MC_DO_DURATION[1] = DO_DURATION[1];
assign _MC_DO_DURATION[0] = DO_DURATION[0];
assign _MC_EVENTS_DELAY[5] = EVENTS_DELAY[5];
assign _MC_EVENTS_DELAY[4] = EVENTS_DELAY[4];
assign _MC_EVENTS_DELAY[3] = EVENTS_DELAY[3];
assign _MC_EVENTS_DELAY[2] = EVENTS_DELAY[2];
assign _MC_EVENTS_DELAY[1] = EVENTS_DELAY[1];
assign _MC_EVENTS_DELAY[0] = EVENTS_DELAY[0];
assign _MC_4WINDOW_CLKS[5] = FOUR_WINDOW_CLOCKS[5];
assign _MC_4WINDOW_CLKS[4] = FOUR_WINDOW_CLOCKS[4];
assign _MC_4WINDOW_CLKS[3] = FOUR_WINDOW_CLOCKS[3];
assign _MC_4WINDOW_CLKS[2] = FOUR_WINDOW_CLOCKS[2];
assign _MC_4WINDOW_CLKS[1] = FOUR_WINDOW_CLOCKS[1];
assign _MC_4WINDOW_CLKS[0] = FOUR_WINDOW_CLOCKS[0];
assign _MC_MULTI_REGION = MULTI_REGION;
assign _MC_PHY_CNT_ENAB = PHY_COUNT_ENABLE;
assign _MC_RD_CMD_OFFSET_0[5] = RD_CMD_OFFSET_0[5];
assign _MC_RD_CMD_OFFSET_0[4] = RD_CMD_OFFSET_0[4];
assign _MC_RD_CMD_OFFSET_0[3] = RD_CMD_OFFSET_0[3];
assign _MC_RD_CMD_OFFSET_0[2] = RD_CMD_OFFSET_0[2];
assign _MC_RD_CMD_OFFSET_0[1] = RD_CMD_OFFSET_0[1];
assign _MC_RD_CMD_OFFSET_0[0] = RD_CMD_OFFSET_0[0];
assign _MC_RD_CMD_OFFSET_1[5] = RD_CMD_OFFSET_1[5];
assign _MC_RD_CMD_OFFSET_1[4] = RD_CMD_OFFSET_1[4];
assign _MC_RD_CMD_OFFSET_1[3] = RD_CMD_OFFSET_1[3];
assign _MC_RD_CMD_OFFSET_1[2] = RD_CMD_OFFSET_1[2];
assign _MC_RD_CMD_OFFSET_1[1] = RD_CMD_OFFSET_1[1];
assign _MC_RD_CMD_OFFSET_1[0] = RD_CMD_OFFSET_1[0];
assign _MC_RD_CMD_OFFSET_2[5] = RD_CMD_OFFSET_2[5];
assign _MC_RD_CMD_OFFSET_2[4] = RD_CMD_OFFSET_2[4];
assign _MC_RD_CMD_OFFSET_2[3] = RD_CMD_OFFSET_2[3];
assign _MC_RD_CMD_OFFSET_2[2] = RD_CMD_OFFSET_2[2];
assign _MC_RD_CMD_OFFSET_2[1] = RD_CMD_OFFSET_2[1];
assign _MC_RD_CMD_OFFSET_2[0] = RD_CMD_OFFSET_2[0];
assign _MC_RD_CMD_OFFSET_3[5] = RD_CMD_OFFSET_3[5];
assign _MC_RD_CMD_OFFSET_3[4] = RD_CMD_OFFSET_3[4];
assign _MC_RD_CMD_OFFSET_3[3] = RD_CMD_OFFSET_3[3];
assign _MC_RD_CMD_OFFSET_3[2] = RD_CMD_OFFSET_3[2];
assign _MC_RD_CMD_OFFSET_3[1] = RD_CMD_OFFSET_3[1];
assign _MC_RD_CMD_OFFSET_3[0] = RD_CMD_OFFSET_3[0];
assign _MC_RD_DURATION_0[5] = RD_DURATION_0[5];
assign _MC_RD_DURATION_0[4] = RD_DURATION_0[4];
assign _MC_RD_DURATION_0[3] = RD_DURATION_0[3];
assign _MC_RD_DURATION_0[2] = RD_DURATION_0[2];
assign _MC_RD_DURATION_0[1] = RD_DURATION_0[1];
assign _MC_RD_DURATION_0[0] = RD_DURATION_0[0];
assign _MC_RD_DURATION_1[5] = RD_DURATION_1[5];
assign _MC_RD_DURATION_1[4] = RD_DURATION_1[4];
assign _MC_RD_DURATION_1[3] = RD_DURATION_1[3];
assign _MC_RD_DURATION_1[2] = RD_DURATION_1[2];
assign _MC_RD_DURATION_1[1] = RD_DURATION_1[1];
assign _MC_RD_DURATION_1[0] = RD_DURATION_1[0];
assign _MC_RD_DURATION_2[5] = RD_DURATION_2[5];
assign _MC_RD_DURATION_2[4] = RD_DURATION_2[4];
assign _MC_RD_DURATION_2[3] = RD_DURATION_2[3];
assign _MC_RD_DURATION_2[2] = RD_DURATION_2[2];
assign _MC_RD_DURATION_2[1] = RD_DURATION_2[1];
assign _MC_RD_DURATION_2[0] = RD_DURATION_2[0];
assign _MC_RD_DURATION_3[5] = RD_DURATION_3[5];
assign _MC_RD_DURATION_3[4] = RD_DURATION_3[4];
assign _MC_RD_DURATION_3[3] = RD_DURATION_3[3];
assign _MC_RD_DURATION_3[2] = RD_DURATION_3[2];
assign _MC_RD_DURATION_3[1] = RD_DURATION_3[1];
assign _MC_RD_DURATION_3[0] = RD_DURATION_3[0];
assign _MC_SPARE = SPARE;
assign _MC_SYNC_MODE = SYNC_MODE;
assign _MC_WR_CMD_OFFSET_0[5] = WR_CMD_OFFSET_0[5];
assign _MC_WR_CMD_OFFSET_0[4] = WR_CMD_OFFSET_0[4];
assign _MC_WR_CMD_OFFSET_0[3] = WR_CMD_OFFSET_0[3];
assign _MC_WR_CMD_OFFSET_0[2] = WR_CMD_OFFSET_0[2];
assign _MC_WR_CMD_OFFSET_0[1] = WR_CMD_OFFSET_0[1];
assign _MC_WR_CMD_OFFSET_0[0] = WR_CMD_OFFSET_0[0];
assign _MC_WR_CMD_OFFSET_1[5] = WR_CMD_OFFSET_1[5];
assign _MC_WR_CMD_OFFSET_1[4] = WR_CMD_OFFSET_1[4];
assign _MC_WR_CMD_OFFSET_1[3] = WR_CMD_OFFSET_1[3];
assign _MC_WR_CMD_OFFSET_1[2] = WR_CMD_OFFSET_1[2];
assign _MC_WR_CMD_OFFSET_1[1] = WR_CMD_OFFSET_1[1];
assign _MC_WR_CMD_OFFSET_1[0] = WR_CMD_OFFSET_1[0];
assign _MC_WR_CMD_OFFSET_2[5] = WR_CMD_OFFSET_2[5];
assign _MC_WR_CMD_OFFSET_2[4] = WR_CMD_OFFSET_2[4];
assign _MC_WR_CMD_OFFSET_2[3] = WR_CMD_OFFSET_2[3];
assign _MC_WR_CMD_OFFSET_2[2] = WR_CMD_OFFSET_2[2];
assign _MC_WR_CMD_OFFSET_2[1] = WR_CMD_OFFSET_2[1];
assign _MC_WR_CMD_OFFSET_2[0] = WR_CMD_OFFSET_2[0];
assign _MC_WR_CMD_OFFSET_3[5] = WR_CMD_OFFSET_3[5];
assign _MC_WR_CMD_OFFSET_3[4] = WR_CMD_OFFSET_3[4];
assign _MC_WR_CMD_OFFSET_3[3] = WR_CMD_OFFSET_3[3];
assign _MC_WR_CMD_OFFSET_3[2] = WR_CMD_OFFSET_3[2];
assign _MC_WR_CMD_OFFSET_3[1] = WR_CMD_OFFSET_3[1];
assign _MC_WR_CMD_OFFSET_3[0] = WR_CMD_OFFSET_3[0];
assign _MC_WR_DURATION_0[5] = WR_DURATION_0[5];
assign _MC_WR_DURATION_0[4] = WR_DURATION_0[4];
assign _MC_WR_DURATION_0[3] = WR_DURATION_0[3];
assign _MC_WR_DURATION_0[2] = WR_DURATION_0[2];
assign _MC_WR_DURATION_0[1] = WR_DURATION_0[1];
assign _MC_WR_DURATION_0[0] = WR_DURATION_0[0];
assign _MC_WR_DURATION_1[5] = WR_DURATION_1[5];
assign _MC_WR_DURATION_1[4] = WR_DURATION_1[4];
assign _MC_WR_DURATION_1[3] = WR_DURATION_1[3];
assign _MC_WR_DURATION_1[2] = WR_DURATION_1[2];
assign _MC_WR_DURATION_1[1] = WR_DURATION_1[1];
assign _MC_WR_DURATION_1[0] = WR_DURATION_1[0];
assign _MC_WR_DURATION_2[5] = WR_DURATION_2[5];
assign _MC_WR_DURATION_2[4] = WR_DURATION_2[4];
assign _MC_WR_DURATION_2[3] = WR_DURATION_2[3];
assign _MC_WR_DURATION_2[2] = WR_DURATION_2[2];
assign _MC_WR_DURATION_2[1] = WR_DURATION_2[1];
assign _MC_WR_DURATION_2[0] = WR_DURATION_2[0];
assign _MC_WR_DURATION_3[5] = WR_DURATION_3[5];
assign _MC_WR_DURATION_3[4] = WR_DURATION_3[4];
assign _MC_WR_DURATION_3[3] = WR_DURATION_3[3];
assign _MC_WR_DURATION_3[2] = WR_DURATION_3[2];
assign _MC_WR_DURATION_3[1] = WR_DURATION_3[1];
assign _MC_WR_DURATION_3[0] = WR_DURATION_3[0];

// (no optinv attribute configured pin in this block)

// (no cfg_const attribute configured pin in this block)

// (no programming attribute configured pin in this block)

// (no unconnected netlist pins in this block)

// (no optinv attribute in this block)
// (no cfg_const attribute in this block)
// (no binary or hexadecimal attribute in this block)

// (no programming attribute in this block)
// (no programming attribute in this block)

// (no software attribute configured memory cell in this block to force)
// (no optinv attribute configured memory cell in this block to force)
// (no cfg_const attribute configured memory cell in this block to force)
// (no programming attribute configured memory cell in this block to force)

// (no software attribute configured memory cell in this block to release)
// (no optinv attribute configured memory cell in this block to release)
// (no cfg_const attribute configured memory cell in this block to release)
// (no programming attribute configured memory cell in this block to release)

xil_phy_control_mod0 global_events ();

xil_phy_control_mod1 BUT (
_PHY_Clk, _PHY_Ctl_Mstr_Empty, _PHY_Ctl_Wr_Enable, _PHY_Ctl_Wd,
_PHY_Ctl_Empty, _PHY_Ctl_Full_N, _PHY_Ctl_AlmostFull_N, _PHY_Ctl_Ready_N,
_Mem_Ref_Clk, _PLL_Lock, _RefDLL_Lock, _Reset, _gwe, _cfg_reset, _grestore,
_Sync_In, _Read_Calib_Enable, _Write_Calib_Enable, _MC_CLK_RATIO,
_MC_DATA_CTL_A_N, _MC_DATA_CTL_B_N, _MC_DATA_CTL_C_N, _MC_DATA_CTL_D_N,
_Aux_Output_N, _MC_AO_WRLVL_EN, _MC_WR_CMD_OFFSET_0, _MC_WR_DURATION_0,
_MC_RD_CMD_OFFSET_0, _MC_RD_DURATION_0, _MC_WR_CMD_OFFSET_1,
_MC_WR_DURATION_1, _MC_RD_CMD_OFFSET_1, _MC_RD_DURATION_1,
_MC_WR_CMD_OFFSET_2, _MC_WR_DURATION_2, _MC_RD_CMD_OFFSET_2,
_MC_RD_DURATION_2, _MC_WR_CMD_OFFSET_3, _MC_WR_DURATION_3,
_MC_RD_CMD_OFFSET_3, _MC_RD_DURATION_3, _MC_CMD_OFFSET, _MC_AO_TOGGLE,
_PC_Enable_Calib, _In_Burst_Pending, _In_Rank_A, _In_Rank_B, _In_Rank_C,
_In_Rank_D, _Out_Burst_Pending, _MC_BURST_MODE, _MC_CO_DURATION,
_MC_DI_DURATION, _MC_DO_DURATION, _MC_EVENTS_DELAY, _MC_4WINDOW_CLKS,
_MC_PHY_CNT_ENAB, _MC_DISABLE_SEQMATCH, _MC_SYNC_MODE, _MC_SPARE,
_MC_MULTI_REGION, _Test_Input, _Test_Select, _Test_Output_N, _Scan_Enable_N
);

endmodule

//protect end

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