【verilog学习18】HDLBits：Circuits_Sequential Logic_Counters

I four-bit binary counter (Count15)

1.代码编写

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk) begin
        q <= (reset)? 4'd0:q+4'd1;
    end
endmodule

2.提交结果

Success

3.题目分析

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

4bit二进制计数器，周期为16，同步、高电平置位。
（得益于周期为16这一特殊条件 4‘b1111+4’b0001=4’b0000，所以条件语句的(q4’b1111 | reset1’b1)? 前半部分可省略）。

II Decade counter (Count 10)

1.代码编写

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk)
        q <= (q==4'd9|reset)? 4'd0:q+4'd1;
endmodule

2.提交结果

Success

3.题目分析

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

与第II题做对比，这里(q==4’d9|reset)?的前半部分条件便不可省略。

III Decade counter again (Count1to10)

1.代码编写

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q <= 4'd1;
        else
            q <= (q==4'd10)? 4'd1:q+4'd1;
    end
endmodule

2.提交结果

Success

3.题目分析

Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

设计一个1~10计数器，同步、高电平置位。

IV slow decade counter (countslow)

1.代码编写

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q <= 4'd0;
        else if(slowena)
            q <= (q==4'd9)? 4'd0:q+4'd1;
        else
            q <= q;
    end
endmodule

2.提交结果

Success

3.题目分析

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

• Hint…
• This is a regular decade counter with an enable control signal
  相当于十进制计数器加一个使能信号。

V counter 1-12 (Exams/ece241 2014 q7a 没看懂题)

1.代码编写

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
	assign c_enable = enable; //使能端
    assign c_load = reset|enable&Q==4'd12; //当reset是或计数上限且使能时才可加载数据
    assign c_d = c_load;
        count4 the_counter (clk, c_enable, c_load, c_d,Q );

endmodule

2.提交结果

Success

3.题目分析

$没看懂，不会分析。。。$
Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1
Enable Set high for the counter to run
Clk Positive edge-triggered clock input
Q[3:0] The output of the counter
c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
logic gates
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter’s enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

VI Counter 1000 (Exams/ece241 2014 q7b)

1.代码编写

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire [3:0] q0,q1,q2;
    always@(*) begin //clk是连接在BCDCounter的，这里对于每个BCDCounter的控制用连续赋值即可。否则延迟一个clk cycle。
    	if(reset)
    		c_enable=3'b000;
    	else begin
        	c_enable[0]=1'b1;
        	if(q0==4'd9)
            	c_enable[1]=1'b1;
	        else
    	        c_enable[1]=1'b0;
        	if(q1==4'd9&&q0==4'd9)
            	c_enable[2]=1'b1;
	        else
    	        c_enable[2]=1'b0;
        end
    end
    assign OneHertz=(q0==4'd9&q1==4'd9&q2==4'd9);
    bcdcount counter0 (clk, reset, c_enable[0],q0/*, ... */);
    bcdcount counter1 (clk, reset, c_enable[1],q1/*, ... */);
    bcdcount counter2 (clk, reset, c_enable[2],q2/*, ... */);
	
endmodule

2.提交结果

Success

3.题目分析

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
通过三个BCD计数器（每个计数器必须直接连接1000hz的clk），来实现一个1hz的信号。这个信号用作使能输入，来实现一个数字挂钟。基于他的应用，我们只需隔999个clk周期，置OneHertz信号为1，保持一个clk周期（每1000个clk周期置OneHertz信号为1一次）。
其实就是完成一个分频的功能。
波形如下：

VII 4-digit decimal counter (Countbcd)

1.代码编写

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    always@(*)begin
        if(q[3:0]==4'd9)
            ena[1]=1'b1;
        else
            ena[1]=1'b0;
        if(q[3:0]==4'd9&q[7:4]==4'd9)
            ena[2]=1'b1;
        else
            ena[2]=1'b0;
        if(q[3:0]==4'd9&q[7:4]==4'd9&q[11:8]==4'd9)
            ena[3]=1'b1;
        else
            ena[3]=1'b0;
    end
    BCDcounter instance0(.clk(clk),.reset(reset),.ena(1'b1),.q(q[3:0]));
    BCDcounter instance1(.clk(clk),.reset(reset),.ena(ena[1]),.q(q[7:4]));
    BCDcounter instance2(.clk(clk),.reset(reset),.ena(ena[2]),.q(q[11:8]));
    BCDcounter instance3(.clk(clk),.reset(reset),.ena(ena[3]),.q(q[15:12]));                                                                                                     
endmodule

module BCDcounter (
    input clk,
    input reset,
    input ena,
    output [3:0] q);
    always@(posedge clk) begin
        if(~ena&~reset) //未使能&未置位，维持原输出
            q <= q;
        else // 使能，按规则加、进位、置位
            q <= (q==4'd9|reset)? 4'd0:q+4'd1;
    end
endmodule

2.提交结果

Success
波形：

3.题目分析

用4个BCD计数器设计一个四位十进制计数器。
每一个BCDcounter正常设计，同步高电平置位，逢9置位。top_module按照每一位的数值输出控制每一个BCDcounter的使能信号即可，这里用always@(*)组合逻辑，连续赋值，满足条件时立即改变。

VIII 12-hour clock ()

1.代码编写

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    always@(posedge clk) begin
        if(reset) begin
            hh <= 8'h12;
            mm <= 8'h00;
            ss <= 8'h00;
            pm <= 1'b0;
        end
        else if(ena) begin
            if(ss[3:0]==4'h9) begin
                ss[3:0] <= 4'h0;
                if(ss[7:4]==4'h5) begin
                    ss[7:4] <= 4'h0;
                    if(mm[3:0]==4'h9) begin
                        mm[3:0] <= 4'h0;
                        if(mm[7:4]==4'h5) begin
                            mm[7:4] <= 4'h0;
                            //hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
                            if(hh==8'h9) 
                                hh <= 8'h10;
                            else if(hh==8'h11) begin
                                hh <= 8'h12;
                                pm <= ~pm;
                            end   
                            else if(hh==8'h12) 
                                hh <= 8'h01;
                            else
                                hh <= hh+8'h1;
                            //hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
                        end
                        else
                            mm[7:4]=mm[7:4]+4'h1;
                    end
                    else
                        mm[3:0]=mm[3:0]+4'h1;
                end
                else
                    ss[7:4]=ss[7:4]+4'h1;
            end
            else
                ss[3:0]=ss[3:0]+4'h1;
        end
    end
endmodule

2.提交结果

Success
wave:

3.题目分析

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

hh,mm,ss都是由两个BCD码组成的，BCD码用四位二进制（1位16进制）表示1位十进制数，所以要注意进位的规则。